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datasheet v2.1 deutron electronics corp. data sheet 1g bits ddr2 sdram p3r1ge3jgf(128m words 8 bits) P3R1GE4JGF(64m words 16 bits) specifications ? density: 1g bits ? organization ? 16m words 8 bits 8 banks (p3r1ge3jgf) ? 8m words 16 bits 8 banks (P3R1GE4JGF) ? package ? 60-ball fbga (p3r1ge3jgf) ? 84-ball fbga (P3R1GE4JGF) ? lead-free (rohs compliant) and halogen-free ? power supply: vdd, vddq = 1.8v 0.1v ? data rate ? 800mbps (max.) ? 1kb page size (p3r1ge3jgf) ? row address: a0 to a13 ? column address: a0 to a9 ? 2kb page size (P3R1GE4JGF) ? row address: a0 to a12 ? column address: a0 to a9 ? eight internal banks for concurrent operation ? interface: sstl_18 ? burst lengths (bl): 4, 8 ? burst type (bt): ? sequential (4, 8) ? interleave (4, 8) ? /cas latency (cl): 3, 4, 5, 6 ? precharge: auto precharge option for each burst access ? driver strength: normal, weak ? refresh: auto-refresh, self-refresh ? refresh cycles: 8192 cycles/64ms ? average refresh period 7.8 s at 0 c tc + 85c 3.9 s at + 85c < tc + 95c ? operating case temperature range ? tc = 0 c to +95 c features ? double-data-rate architecture; two data transfers per clock cycle ? the high-speed data transfer is realized by the 4 bits prefetch pipelined architecture ? bi-directional differential data strobe (dqs and /dqs) is transmitted/received with data for capturing data at the receiver ? dqs is edge-aligned with data for reads; center- aligned with data for writes ? differential clock inputs (ck and /ck) ? dll aligns dq and dqs transitions with ck transitions ? commands entered on each positive ck edge; data and data mask referenced to both edges of dqs ? data mask (dm) for write data ? posted /cas by programmable additive latency for better command and data bus efficiency ? programmable rdqs, /rdqs output for making 8 organization compatible to 4 organization ? /dqs, (/rdqs) can be disabled for single-ended data strobe operation ? off-chip driver (ocd) impeda nce adjustment is not supported.
p3r1ge3jgf, P3R1GE4JGF d . 2 ordering information part number die revision organization (words bits) internal banks speed bin (cl-trcd-trp) packag p3r1ge3jgf-g8e j 128m x 8 8 ddr2-800 (5-5-5) 60-ball fbga P3R1GE4JGF-g 64m 16 ddr2-800 (5-5-5) 84-ball fbga part number 2009/7/15 2 3 7 1 11 9 6 device body 12. green 10 8 4,5 13 speed 13. speed 12 10. package type f:fbga 7. organization 3:x8,4:x16 3. interface r:1.8v sstl_18 4,5.density 2. memory style (dram) 6. synchronous dram 1. mira dram 9. process generation 8. die rev. p 3 r e j g - 8e g f 1g 3 8e: ddr2-800 u 14. ett grade 14
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. 3 pin configurations /xxx indicates active low signal. a b c d e f g h j k l vdd 1 vddq vdd vddl 2 vssq udm dq14 dq9 vssq dq12 nc vref 3 vss nc vddq dq11 vss cke /we vss 7 vssq udqs vddq dq10 vssq /ras 8 /udqs vssq dq15 dq8 vssq dq13 /ldqs /ck m n p r vdd a12 nc nc nc 9 vddq vddq dq6 dq4 vssq dq1 vddq vssq ldm vddq dq3 ldqs vddq vssq dq0 vddq dq2 vssq dq5 dq7 vddq vssdl ck vdd vss a10 a3 a7 a1 a5 a9 a2 a6 a11 a0 a4 a8 vdd vss (top view) 84-ball fbga ba0 ba1 /cas /cs ba2 odt ( 16 organization) ( 8 organization) vdd 1 dq6 vddq dq4 vddl vss vdd 2 nu/ /rdqs vssq dq1 vssq vref cke ba0 a10 a3 a7 a12 3 vss dm/rdqs vddq dq3 vss /we ba1 a1 a5 a9 nc 7 vssq dqs vddq dq2 vssdl /ras /cas a2 a6 a11 nc 8 /dqs vssq dq0 vssq ck /ck /cs a0 a4 a8 a13 9 vddq dq7 vddq dq5 vdd vdd vss (top view) 60-ball fbga ba2 odt a b c d e f g h j k l pin name function pin name function a0 to a13 address inputs odt odt control ba0, ba1, ba2 bank select vdd supply voltage for internal circuit dq0 to dq15 data input/output vss ground for internal circuit dqs, /dqs, udqs, /udqs, ldqs, /ldqs differential data strobe vddq supply voltage for dq circuit rdqs, /rdqs differential data strobe for read vssq ground for dq circuit /cs chip select vref input reference voltage /ras, /cas, /we command input vddl supply voltage for dll circuit cke clock enable vssdl ground for dll circuit ck, /ck differential clock input nc* 1 no connection dm, udm, ldm write data mask nu* 2 not usable notes: 1. not internally connected with die. 2. dont connect. internally connected.
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. 9 max. parameter symbol grade 8 16 unit test condition auto-refresh current idd5 120 120 ma tck = tck (idd); refresh command at every trfc (idd) interval; cke is h, /cs is h between valid commands; other control and address bus inputs are switching; data bus inputs are switching self-refresh current idd6* 7 10 10 ma self-refresh mode; ck and /ck at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating operating current (bank interleaving) idd7 130 170 ma all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = trcd (idd) ?1 tck (idd); tck = tck (idd), trc = trc (idd), trrd = trrd (idd), tfaw = tfaw (idd), trcd = 1 tck (idd); cke is h, /cs is h between valid commands; address bus inputs are stable during deselects; data pattern is same as idd4w; notes: 1. idd specificati ons are tested after the device is properly initialized. 2. input slew rate is specifie d by ac input test condition. 3. idd parameters are spec ified with odt disabled. 4. data bus consists of dq, dm, dqs, /dqs, rdqs and /rdqs. idd values must be met with all combinations of emrs bits 10 and 11. 5. definitions for idd l is defined as vin vil (ac) (max.) h is defined as vin vih (ac) (min.) stable is defined as inputs stable at an h or l level floating is defined as inputs at vref = vddq/2 switching is defined as: inputs changing between h and l every other clock cycle (once per two clocks) for address and control signals, and inputs changing between h and l every othe r data transfer (once per clock) for dq sig nals not including masks or strobes. 6. refer to ac timing for idd test conditions. 7. idd6 will increase by 80% if tc +85c and high temperature self-refresh rate option is enabled.
p3r1ge3jgf, P3R1GE4JGF d 5 electrical specifications ? all voltages are referenced to vss (gnd) ? execute power-up and initialization sequence before proper device oper ation is achieved. absolute maximum ratings parameter symbol rating unit notes power supply voltage vdd ?1.0 to +2.3 v 1 power supply voltage for output vddq ?0.5 to +2.3 v 1 input voltage vin ?0.5 to +2.3 v 1 output voltage vout ?0.5 to +2.3 v 1 storage temperature tstg ?55 to +100 c 1, 2 power dissipation pd 1.0 w 1 short circuit output current iout 50 ma 1 notes: 1. stresses greater than th ose listed under abso lute maximum ratings m ay cause permanent damage to the device. this is a stress rating onl y and functi onal operation of the devic e at these or an y other conditions above those indicated in the operational sectio ns of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface te mperature on the center/t op side of the dram. caution exposing the device to stress ab ove those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specifi cation. expo sure to absolute maximum rating conditions for extended periods may affect device reliability. operating temperature condition parameter symbol rating unit notes operating case temperature tc 0 to +95 c 1, 2 notes: 1. operating tem perature is the case surface temperat ure on the center/top side of the dram. 2. supporting 0c to +85c with full ac and dc specifications. supporting 0c to + 85c and being able to exte nd to + 95c with doubling auto-refresh commands in frequency to a 32ms period (trefi = 3.9 s) and high er temperature self-re fresh entry via a7 "1" o n emrs (2).
p3r1ge3jgf, P3R1GE4JGF d 6 recommended dc operating conditions (sstl_18) parameter symbol min. typ. max. unit notes supply voltage vdd 1.7 1.8 1.9 v 4 supply voltage for output vddq 1.7 1.8 1.9 v 4 input reference voltage vref 0.49 vddq 0.50 vddq 0.51 vddq v 1, 2 termination voltage vtt vref ? 0.04 vref vref + 0.04 v 3 dc input logic high vih (dc) vref + 0.125 ? vddq + 0.3 v dc input logic low vil (dc) ?0.3 ? vref C 0.125 v ac input logic high vih (ac) vref + 0.200 ? ? v ac input logic low vil (ac) ? ? vref ? 0.200 v notes: 1. the value of vref may be selected by the user to provide optimum noise margin in the system. typically the value of vref is expected to be about 0.5 vddq of the transmitting device and vref are expected to track variations in vddq. 2. peak to peak ac noise on vref may not exceed 2% vref (dc). 3. vtt of transmitting device must track vref of receiving device. 4. vddq tracks with vdd, vddl tracks with vdd. ac parameters are measur ed with vdd, vddq and vddl tied together.
p3r1ge3jgf, P3R1GE4JGF d 7 ac overshoot/undershoot specification parameter pins specification unit maximum peak amplitude allowed for overshoot command, address, 0.5 v maximum peak amplitude allowed for undershoot cke, odt 0.5 v maximum overshoot area above vdd 0.66 v-ns maximum undershoot area below vss 0.66 v-ns maximum peak amplitude allowed for overshoot ck, /ck 0.5 v maximum peak amplitude allowed for undershoot 0.5 v maximum overshoot area above vdd 0.23 v-ns maximum undershoot area below vss 0.23 v-ns maximum peak amplitude allowed for overshoot dq, dqs, /dqs, 0.5 v maximum peak amplitude allowed for undershoot udqs, /udqs, ldqs, /ldqs, 0.5 v maximum overshoot area above vddq rdqs, /rdqs, dm, udm, ldm 0.23 v-ns maximum undershoot area below vssq 0.23 v-ns maximum amplitude overshoot area undershoot area volts (v) time (ns) vdd, vddq vss, vssq overshoot/undershoot definition
p3r1ge3jgf, P3R1GE4JGF d 8 dc characteristics 1 (tc = 0 c to +85 c, vdd, vddq = 1.8v 0.1v) max. parameter symbol grade 8 16 unit test condition operating current (act-pre) idd0 45 55 ma one bank; tck = tck (idd), trc = trc (idd), tras = tras min.(idd); cke is h, /cs is h between valid commands; address bus inputs are switching; data bus inputs are switching operating current (act-read-pre) idd1 55 70 ma one bank; iout = 0ma; bl = 4, cl = cl(idd), al = 0; tck = tck (idd), trc = trc (idd), tras = tras min.(idd); trcd = trcd (idd); cke is h, /cs is h between valid commands; address bus inputs are switching; data pattern is same as idd4w precharge power- down standby current idd2p 10 10 ma all banks idle; tck = tck (idd); cke is l; other control and address bus inputs are stable; data bus inputs are floating precharge quiet standby current idd2q 18 18 ma all banks idle; tck = tck (idd); cke is h, /cs is h; other control and address bus inputs are stable; data bus inputs are floating idle standby current idd2n 20 20 ma all banks idle; tck = tck (idd); cke is h, /cs is h; other control and address bus inputs are switching; data bus inputs are switching idd3p-f 25 25 ma fast pdn exit mrs (12) = 0 active power-down standby current idd3p-s 13 13 ma all banks open; tck = tck (idd); cke is l; other control and address bus inputs are stable; data bus inputs are floating slow pdn exit mrs (12) = 1 active standby current idd3n 40 40 ma all banks open; tck = tck (idd), tras = tras max.(idd), trp = trp (idd); cke is h, /cs is h between valid commands; other control and address bus inputs are switching; data bus inputs are switching operating current (burst read operating) idd4r 90 115 ma all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; tck = tck (idd), tras = tras max.(idd), trp = trp (idd); cke is h, /cs is h between valid commands; address bus inputs are switching; data pattern is same as idd4w operating current (burst write operating) idd4w 95 125 ma all banks open, continuous burst writes; bl = 4, cl = cl(idd), al = 0; tck = tck (idd), tras = tras max.(idd), trp = trp (idd); cke is h, /cs is h between valid commands; address bus inputs are switching; data bus inputs are switching
p3r1ge3jgf, P3R1GE4JGF d 9 max. parameter symbol grade 8 16 unit test condition auto-refresh current idd5 120 120 ma tck = tck (idd); refresh command at every trfc (idd) interval; cke is h, /cs is h between valid commands; other control and address bus inputs are switching; data bus inputs are switching self-refresh current idd6* 7 10 10 ma self-refresh mode; ck and /ck at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating operating current (bank interleaving) idd7 130 170 ma all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = trcd (idd) ?1 tck (idd); tck = tck (idd), trc = trc (idd), trrd = trrd (idd), tfaw = tfaw (idd), trcd = 1 tck (idd); cke is h, /cs is h between valid commands; address bus inputs are stable during deselects; data pattern is same as idd4w; notes: 1. idd specificati ons are tested after the device is properly initialized. 2. input slew rate is specifie d by ac input test condition. 3. idd parameters are spec ified with odt disabled. 4. data bus consists of dq, dm, dqs, /dqs, rdqs and /rdqs. idd values must be met with all combinations of emrs bits 10 and 11. 5. definitions for idd l is defined as vin vil (ac) (max.) h is defined as vin vih (ac) (min.) stable is defined as inputs stable at an h or l level floating is defined as inputs at vref = vddq/2 switching is defined as: inputs changing between h and l every other clock cycle (once per two clocks) for address and control signals, and inputs changing between h and l every othe r data transfer (once per clock) for dq sig nals not including masks or strobes. 6. refer to ac timing for idd test conditions. 7. idd6 will increase by 80% if tc +85c and high temperature self-refresh rate option is enabled.
p3r1ge3jgf, P3R1GE4JGF d document : ver.2.1 deutron electronics corp. 10 ac timing for idd test conditions for purposes of idd testing, the foll owing parameters are to be utilized. ddr2-800 parameter 5-5-5 unit cl (idd) 5 tck trcd (idd) 12.5 ns trc (idd) 57.5 ns trrd (idd)- 8 7.5 ns trrd (idd)- 16 10 ns tfaw (idd)- 8 35 ns tfaw (idd)- 16 45 ns tck (idd) 2.5 ns tras (min.)(idd) 45 ns tras (max.)(idd) 70000 ns trp (idd) 12.5 ns trfc (idd) 127.5 ns idd7 timing patterns for 8 banks the detailed timings are shown in the idd7 timing patterns for 8 banks tables. [ 8 organization] speed bins timing patterns ddr2-800 a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d a4 ra4 d a5 ra5 d a6 ra6 d a7 ra7 d d d [ 16 organization] speed bins timing patterns ddr2-800 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d d remark: a = active. ra = read wi th auto precharge. d = deselect notes: 1. all banks are being interleaved at minimum trc (idd) without violating trrd (idd) and tfaw (idd) using a burst length = 4. 2. control and address bus inputs are stable during deselects. 3. iout = 0ma.
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 11 dc characteristics 2 (tc = 0 c to +85 c, vdd, vddq = 1.8v 0.1v) parameter symbol value unit notes input leakage current ? ili? 2 a vdd vin vss output leakage current ? ilo ? 5 a vddq vout vss minimum required output pull-up under ac test load voh vtt + 0.603 v maximum required output pull-down under ac test load vol vtt ? 0.603 v output timing measurement reference level votr 0.5 vddq v 1 output minimum sink dc current iol +13.4 ma 3, 4 output minimum source dc current ioh ?13.4 ma 2, 4 notes: 1. the vddq of the dev ice under test is referenced. 2. vddq = 1.7v; vout = 1.42v. 3. vddq = 1.7v; vout = 0.28v. 4. the dc value of vref applied to the receiving device is expected to be set to vtt. dc characteristics 3 (tc = 0 c to +85 c, vdd, vddq = 1.8v 0.1v) parameter symbol min. max. unit notes ac differential input voltage vid (ac) 0.5 vddq + 0.6 v 1, 2 ac differential cross point voltage vix (ac) 0.5 vddq ? 0.175 0.5 vddq + 0.175 v 2 ac differential cross point voltage vox (ac) 0.5 vddq ? 0.125 0.5 vddq + 0.125 v 3 notes: 1. vid (ac) specifies the inpu t differential voltage |vtr -vcp| requir ed for switching, where vtr is the tru e input signal (such as ck, d qs, rdqs) and vcp is t he complementary input signal (such as /ck, /dqs, /rdqs). the minimum value is equal to vih (ac) ? vil (ac). 2. the typical value of vix (a c) is expected to be about 0.5 vddq of the transmitting device and vix (ac) is expected to track variations in vddq. vix (ac) i ndicates the voltage at which differential input signals must cross. 3. the typical value of vo x (ac) is e xpected to be a bout 0.5 vddq of the transmit ting device and vox (ac) is expected to track variations in vddq. vox (ac) indicates the vo ltage at which differential output signals must cross. crossing point vssq vtr vcp vid vix or vox vddq differential signal levels* 1, 2
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 12 odt dc electrical characteristics (tc = 0 c to +85 c, vdd, vddq = 1.8v 0.1v) parameter symbol min. typ. max. unit note rtt effective impedance value for emrs (1) (a6, a2) = 0, 1 ; 75 ? rtt1 (eff) 60 75 90 ? 1 rtt effective impedance value for emrs (1) (a6, a2) = 1, 0 ; 150 ? rtt2 (eff) 120 150 180 ? 1 rtt effective impedance value for emrs (1) (a6, a2) = 1, 1 ; 50 ? rtt3 (eff) 40 50 60 ? 1 deviation of vm with respect to vddq/2 ? vm ?6 ? +6 % 1 note: 1. test condition for rtt measurements. measurement definition for rtt (eff) apply vih (ac) and vil (ac) to test pin separately, then measure current i(vih (ac)) and i(vil (ac)) respectively. vih (ac), and vddq values defined in sstl _18. ))(())(( )()( )( acviliacvihi acvilacvih effrtt ? ? = measurement definition for ? vm measure voltage (vm) at test pin (midpoint) with no load. 1001 2 ? ? ? ? ? ? ? =? vddq vm vm pin capacitance (ta = 25 c, vdd, vddq = 1.8v 0.1v) parameter symbol pins min. max. unit notes clk input pin capacitance cck ck, /ck 1.0 2.0 pf 1 input pin capacitance cin /ras, /cas, /we, /cs, cke, odt, address 1.0 1.75 pf 1 input/output pin capacitance ci/o dq, dqs, /dqs, udqs, /udqs, ldqs, /ldqs, rdqs, /rdqs, dm, udm, ldm 2.5 3.5 pf 2 notes: 1. matching within 0.25pf. 2. matching within 0.50pf.
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 13 ac characteristics (tc = 0 c to +85 c, vdd, vddq = 1.8v 0.1v, vss, vssq = 0v) ? new units tck(avg) and nck, are introduced in ddr2-667 or faster. tck(avg): actual tck(avg) of the input clock under operation. nck: one clock cycle of the input clock, counting the actual clock edges. -8e speed bin ddr2-800 (5-5-5) parameter symbol min. max. unit notes active to read or write command delay trcd 12.5 ? ns precharge command period trp 12.5 ? ns active to active/auto-refresh command time trc 57.5 ? ns dq output access time from ck, /ck tac ?400 + 400 ps 10 dqs output access time from ck, /ck tdqsck ?350 + 350 ps 10 ck high-level width tch (avg) 0.48 0.52 tck (avg) 13 ck low-level width tcl(avg) 0.48 0.52 tck (avg) 13 ck half period thp min. (tcl(abs), tch(abs)) ? ps 6, 13 clock cycle time (cl = 6) tck (avg) 2500 8000 ps 13 (cl = 5) tck (avg) 2500 8000 ps 13 (cl = 4) tck (avg) 3750 8000 ps 13 (cl = 3) tck (avg) 5000 8000 ps 13 dq and dm input hold time tdh (base) 125 ? ps 5 dq and dm input setup time tds (base) 50 ? ps 4 control and address input pulse width for each input tipw 0.6 ? tck (avg) dq and dm input pulse width for each input tdipw 0.35 ? tck (avg) data-out high-impedance time from ck, /ck thz ? tac max. ps 10 dqs, /dqs low-impedance time from ck, /c k tlz (dqs) tac min. tac max. ps 10 dq low-impedance time from ck, /ck tlz (dq) 2 tac min. tac max. ps 10 dqs-dq skew for dqs and associated dq signals tdqsq ? 200 ps dq hold skew factor tqhs ? 300 ps 7 dq/dqs output hold time from dqs tqh thp C tqhs ? ps 8 dqs latching rising transitions to associated clock edges tdqss ?0.25 +0.25 tck (avg) dqs input high pulse width tdqsh 0.35 ? tck (avg) dqs input low pulse width tdqsl 0.35 ? tck (avg) dqs falling edge to ck setup time tdss 0.2 ? tck (avg) dqs falling edge hold time from ck tdsh 0.2 ? tck (avg) mode register set command cycle time tmrd 2 ? nck write postamble twpst 0.4 0.6 tck (avg) write preamble twpre 0.35 ? tck (avg) address and control input hold time tih (base) 250 ? ps 5 address and control input setup time tis (base) 175 ? ps 4 read preamble trpre 0.9 1.1 tck (avg) 11 read postamble trpst 0.4 0.6 tck (avg) 12 active to precharge command tras 45 70000 ns active to auto precharge delay trap trcd min. ? ns
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 14 -8e speed bin ddr2-800 (5-5-5) parameter symbol min. max. unit notes active bank a to active bank b command period (p3r1ge3jgf) trrd 7.5 ? ns (P3R1GE4JGF) trrd 10 ? ns four active window period (p3r1ge3jgf) tfaw 35 ? ns (P3R1GE4JGF) tfaw 45 ns /cas to /cas command delay tccd 2 ? nck write recovery time twr 15 ? ns auto precharge write recovery + precharge time tdal wr + ru (trp/tck(avg)) ? nck 1, 9 internal write to read command delay twtr 7.5 ? ns 14 internal read to precharge command delay trtp 7.5 ? ns exit self-refresh to a non-read command txsnr trfc + 10 ? ns exit self-refresh to a read command txsrd 200 ? nck exit precharge power-down to any non-read command txp 2 ? nck exit active power-down to read command txard 2 ? nck 3 exit active power-down to read command (slow exit/low power mode) txards 8 ? al ? nck 2, 3 cke minimum pulse width (high and low pulse width) tcke 3 ? nck mrs command to odt update delay t mod 0 12 ns 15 auto-refresh to active/auto-refresh command time trfc 127.5 ? ns average periodic refresh interval (0 c tc +85 c) trefi ? 7.8 s (+85 c < tc +95 c) trefi ? 3.9 s minimum time clocks remains on after cke asynchronously drops low tdelay tis + tck(avg) + tih ? ns
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 15 notes: 1. for each of the terms above, if not alr eady an integer, round to the next higher integer. 2. al: additive latency. 3. mrs a12 bit defines which active power-down exit timing to be applied. 4. the figures of input w aveform timing 1 a nd 2 are referenced from the inp ut signal crossing at t he vih(ac) level for a rising signal and vil(ac) for a falling signal applied to the device under test. 5. the figures of input w aveform timing 1 a nd 2 are referenced from the inp ut signal crossing at t he vil(dc) level for a rising signal and vih(dc) for a falling signal applied to the device under test. dqs /dqs tds tdh tds tdh vddq vih (ac)(min.) vih (dc)(min.) vil (dc)(max.) vil (ac)(max.) vss vref ck /ck tis tih tis tih vddq vih (ac)(min.) vih (dc)(min.) vil (dc)(max.) vil (ac)(max.) vss vref input waveform timing 1 (tds, tdh) input waveform timing 2 (tis, tih) 6. thp is the minimum of the absolute half period of the actual input clock. thp is an input parameter but not an input specification parameter. it is used in conj unction with tqhs to derive th e dram output timi ng tqh. the value to be used for tqh calculation is determined by the following equation; thp = min ( tch(abs), tcl(abs) ), where, tch(abs) is the minimum of the actual instantaneous clock high time; tcl(abs) is the minimum of the actual instantaneous clock low time; 7. tqhs accounts for: a. the pulse duration distortion of on-chip clock ci rcuits, which represents how well the actual thp at the input is transferred to the output; and b. the worst case push-out of dq s on o ne transition followed by the worst case pu ll-in of dq on th e next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and p-channel to n-channel vari ation of the out put drivers. 8. tqh = thp C tqhs, where: thp is the min imum of the absolut e half pe riod of the actual in put clock; and tqhs is the specification value under the max column. {the less half-pulse width distortion present, the larger the tqh value is; and the larger the valid data eye will be.} examples: a. if the sy stem provides thp of 1315p s into a ddr 2-667 sdram, the dram provides tqh of 975ps (min.) b. if the sy stem provides thp of 1420p s into a ddr 2-667 sdram, the dram provides tqh of 1080ps (min.) 9. ru stands for round up. wr refers to the twr parameter stored in the mrs. 10. when the dev ice is oper ated with input clock jitter, this parameter n eeds to be derate d by the actual terr(6-10per) of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter in to a ddr2-667 sdram has terr(6-10 per) min. = ? 272ps and terr(6-10per) max. = + 293ps, then tdqs ck min.(derated) = tdqsck min. ? terr(6-10per) max. = ? 400ps ? 293ps = ? 693ps and tdqsck max.(derated) = tdqsck max. ? terr(6-10per) min. = 400p s + 272ps = +672ps. similarly, tlz(dq) for ddr2-6 67 derates to tlz(dq) min.(derated) = ? 900ps ? 293ps = ? 1193ps and tlz(dq) max.(derated)= 450ps + 272ps = +722ps.
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 16 11. when the d evice is op erated with input clock jitte r, this parameter n eeds to be der ated by the actu al tjit(per) of the input clock. (output deratings are relative to the sdram input clock.) for example, if the meas ured jitter into a ddr2-667 sdram has tjit (per) min. = ? 72ps and tjit(per) max. = +93ps, then trpre min.(derat ed) = trpre min. + tjit(per) min. = 0.9 tck(avg) ? 72ps = +2178ps and trpre max.(derated) = tr pre max. + tjit(per) max. = 1.1 tck(avg) + 93ps = +2843ps. 12. when the d evice is op erated with input clock jitte r, this parameter n eeds to be der ated by the actu al tjit(duty) of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter int o a ddr2- 667 sdram ha s tjit(duty) min. = ? 72ps and tjit(duty) max. = + 93ps, then trpst min.(derat ed) = trpst min. + tjit(duty) min. = 0.4 tck(avg) ? 72ps = +928ps and trpst max.(derated) = trpst max. + tjit(duty) max. = 0.6 tck(avg) + 93ps = +1592ps. 13. refer to the clock jitter table. 14. twtr is at least two clocks (2 tck or 2 nck) independent of operation frequency. 15. tmod max. = 12ns only applies when changing odt value. (e.g. changing odt value from rtt = 50 ? to rtt = 75 ? .) if odt is disabled and then odt is turned on, tmod max. = 8nck.
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 17 odt ac electrical characteristics parameter symbol min. max. unit notes odt turn-on delay taond 2 2 tck odt turn-on taon tac(min) tac(max) + 700 ps 1, 3 odt turn-on (power-down mode) taonpd tac(min) + 2000 2tck + tac(max) + 1000 ps odt turn-off delay taofd 2.5 2.5 tck 5 odt turn-off taof tac(min) tac(max) + 600 ps 2, 4, 5 odt turn-off (power-down mode) taofpd tac(min) + 2000 2.5tck + tac(max) + 1000 ps odt to power-down entry latency tanpd 3 ? tck odt power-down exit latency taxpd 8 ? tck notes: 1. odt turn on time min is when the device le aves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measured from taond. 2. odt turn off time min is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from taofd. 3. when the dev ice is oper ated with input clock jitter, this parameter n eeds to be derate d by the actual terr(6-10per) of the input clock. (output deratings are relative to the sdram input clock.) 4. when the de vice is oper ated with input clo ck jitter, this paramet er needs to be derated by { ? tjit(duty) max. ? terr(6-10per) max. } and { ? tjit(duty) min. ? terr(6-10per) min. } of the actual input clock.(output deratings are relative to the sdram input clock.) for example, if the measured jitter in to a ddr2-6 67 sdram has terr(6-1 0per) min. = ? 272ps, terr(6-10per) max. = + 293ps , tjit(duty) min. = ? 106ps and tjit (duty) max. = + 94ps, then taof min.(derated) = taof min. + { ? tjit(duty) max. ? terr(6-10per) max. } = ? 450ps + { ? 94ps ? 293ps} = ? 837ps and taof max.(derated) = taof max. + { ? tjit(duty) min. ? terr(6-10per) min. } = 1050ps + { 106ps + 272ps} = +1428ps. 5. for taofd of ddr2-800, the 1/2 clock of nck in the 2.5 nck assumes a tch(avg), average input clock high pulse width of 0.5 relative to tck(avg). taof min. and taof max. should eac h be derate d by the same amount as the actual a mount of tch(avg) offset present at the dram input with respect to 0.5. f or example, if an input clock has a worst case tch( avg) of 0.48, the taof min. should be d erated by subtracting 0.02 tck(avg) from it, whereas if an input clock has a worst case tch(avg) of 0.52, the taof max. should be derated by adding 0.02 tck(avg) to it. therefore, we have; taof min.(derated) = tac min. ? [0.5 ? min.(0.5, tch(avg) min.)] tck(avg) taof max.(derated) = tac max. + 0.6 + [max.(0.5, tch(avg) max.) ? 0.5] tck(avg) or taof min.(derated) = min.(tac min., tac min. ? [0.5 ? tch(avg) min.] tck(avg)) taof max.(derated) = 0.6 + max.(t ac max., tac max. + [tch(avg) max. ? 0.5] tck(avg)) where tch(avg) min. and tch (avg) max. are the minimum and maximum of tch(avg) actually measured at the dram input balls.
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 18 ac input test conditions parameter symbol value unit notes input reference voltage vref 0.5 vddq v 1 input signal maximum peak to peak swing vswing(max.) 1.0 v 1 input signal minimum slew rate slew 1.0 v/ns 2, 3 notes: 1. input waveform timing is ref erenced to the input signal crossing through the vih/il (ac) level a pplied to the device under test. 2. the input signal minimum slew rate is to be maintained over the range from vref to vih(ac) (min.) for rising edges and the range from vref to vil(ac) (ma x.) for falling edges as shown in the below figure. 3. ac timings ar e referenced with input waveforms switching from vil(ac) to vih(ac) on the pos itive transitions and vih(ac) to vil( ac) on the negative transitions. vswing(max.) ? tr ? tf vref ? vil (ac)(max.) ? tf falling slew = vddq vih (ac)(min.) vih (dc)(min.) vil (dc)(max.) vil (ac)(max.) vss vref vih (ac) min. ? vref ? tr rising slew = ac input test signal wave forms vtt measurement point dq rt =25? output load
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 19 clock jitter frequency (mbps) 800 667 parameter symbol min. max. min. max. unit notes average clock period tck (avg) 2500 8000 3000 8000 ps 1 clock period jitter tjit (per) ? 100 100 ? 125 125 ps 5 clock period jitter during dll locking period tjit (per, lck) ? 80 80 ? 100 100 ps 5 cycle to cycle period jitter tjit (cc) ? 200 ? 250 ps 6 cycle to cycle clock period jitter during dll locking period tjit (cc, lck) ? 160 ? 200 ps 6 cumulative error across 2 cycles terr (2per) ? 150 150 ? 175 175 ps 7 cumulative error across 3 cycles terr (3per) ? 175 175 ? 225 225 ps 7 cumulative error across 4 cycles terr (4per) ? 200 200 ? 250 250 ps 7 cumulative error across 5 cycles terr (5per) ? 200 200 ? 250 250 ps 7 cumulative error across n=6,7,8,9,10 cycles terr (6-10per) ? 300 300 ? 350 350 ps 7 cumulative error across n=11, 12,49,50 cycles terr (11-50per) ? 450 450 ? 450 450 ps 7 average high pulse width tch (avg) 0.48 0.52 0.48 0.52 tck (avg) 2 average low pulse width tcl (avg) 0.48 0.52 0.48 0.52 tck (avg) 3 duty cycle jitter tjit (duty) ? 100 100 ? 125 125 ps 4 notes: 1. tck (avg) is calculated as the average clock period across any consecutive 200cycle window. ntckj avgtck n j ? ? ? ? ? ? = = 1 )( n = 200 2. tch (avg) is d efined as the average high pulse width, as calculated across any consecutive 200 high pulses. ))(( )( 1 avgtckntchj avgtch n j ? ? ? ? ? ? = = n = 200 3. tcl (avg) is defined as the average low pulse widt h, as calculated across any consecutive 200 low pulses. ))(( )( 1 avgtckntclj avgtcl n j ? ? ? ? ? ? = = n = 200 4. tjit (duty) is defined as the cumulativ e set of tc h jitter and tcl jitter. tch jitte r is the largest deviati on of any single tch from tch (a vg). tcl jitter is the la rgest deviation of an y single tcl from tcl (avg). tjit (duty) is not subject to production test. tjit (duty) = min./max. of {tjit (ch), tjit (cl)}, where: tjit (ch) = {tch j - tch (avg) where j = 1 to 200} tjit (cl) = {tcl j ? tcl (avg) where j = 1 to 200}
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 20 5. tjit (per) is defined as the largest dev iation of any single tck from tck (avg). tjit (per) = min./max. of { tck j ? tck (avg) where j = 1 to 200} tjit (per) defines the single p eriod jitter when the d ll is alread y locked. tjit (per, lck) uses the same definition for single p eriod jitter, during the dll locking period only. tjit (per) and tjit (per, lck) are not subject to production test. 6. tjit (cc) is defined as the absolute difference in clock period between two consecutive clock cycles: tjit (cc) = max. of |tck j+1 ? tck j | tjit (cc) is defines the c ycle to cycle jitter when the dll is already locked. tjit (cc, lck) uses the s ame definition for cycl e to c ycle jitter, during the dll locki ng period only. tjit (cc) and tjit (cc, lck) are not subject to production test. 7. terr (nper) is defined as the cumulative error ac ross multiple consecutive cycles from tck (avg). terr (nper) is not subject to production test. ))( )( 1 avgtckntckj nperterr n j ? ? ? ? ? ? ? = = 2 n 50 for terr (nper) 8. these parameters are specif ied per the ir average values, however it is understood that the follo wing relationship between the average timing and the abs olute instantaneous timing hold at all times. (minimum and maximum of spec values are to be used for calculations in the table below.) parameter symbol min. max. unit absolute clock period tck (abs) tck (avg) min. + tjit (per) min. tck (avg) max. + tjit (per) max. ps absolute clock high pulse width tch (abs) tch (avg) min. tck (avg) min. + tjit (duty) min. tch (avg) max. tck (avg) max. + tjit (duty) max. ps absolute clock low pulse width tcl (abs) tcl (avg) min. tck (avg) min. + tjit (duty) min. tcl (avg) max. tck (avg) max. + tjit (duty) max. ps example: for ddr2-667, tch(abs) min. = ( 0.48 3000 ps ) - 125ps = 1315ps
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 21 input slew rate derating for all input signals the total tis, tds (setup time) and tih, t dh (hold time) required is cal culated by adding the data sheet tis (bas e), tds (base) and tih (base ), tdh (base) value to th e ? tis, ? tds and ? tih, ? tdh derating value respectively. example: tds (total setup time) = tds (base) + ? tds. setup (tis, tds) nomin al slew rate for a ris ing signal is defined as the slew rate betwee n the last crossing of vref (dc) and the first crossing of vih (ac) min. setup (tis, td s) nominal slew rate for a fall ing signal is defined as the slew rate between the last crossing of vref (dc) and th e firs t crossing of vil (ac) max. if the actual sign al is always earlier than the n ominal slew rate line between sha ded vref (dc) to ac regio n, use nominal slew rate for derating value (see the figure of slew rate definition nominal). if the actual signal is later than the nominal slew rate line anywhere between shaded vref (dc) to ac regio n, the slew rate of a tangent line to the act ual signal from the ac level to dc leve l is used for derating value (see the figure of slew rate definition tangent). hold (tih, tdh ) nominal slew rate for a ri sing signal is defined as th e slew rate between the last crossing of vil (dc) max. and the first crossing of vr ef (dc). hold (tih, tdh) nominal slew rate for a falling si gnal is defined as the slew rate between the last crossing of vih (dc) min. and the first crossing of vref (dc). if the actual signal is always later than the nomi nal slew rate line between sh aded dc lev el to vref (dc) region , use n ominal slew rate for derating value (see the figure of slew rate definition nominal). if the actual signal is earl ier than the nominal slew rate line anywhere between shaded dc to vref (dc) regio n, the slew rate of a tangent line to the actu al signal from the dc level to vref (dc) level is used for derating value (see the figure of slew rate definition tangent). although for s low slew rates the total s etup time mig ht be negative (i.e. a val id input signal will not have reached vih/il (ac) at the time of the rising clock transition) a vali d input signal is still required to complete the transition and reach vih/il (ac). for slew rates in bet ween the values listed in the ta bles below, the derating values may obtained by linear interpolation. these values are typically not subject to production test. they are verified by design and characterization. [derating values of tds/tdh with differential dqs (ddr2-667, 800)] dqs, /dqs differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh unit 2.0 +100 +45 +100 +45 +100 +45 ? ? ? ? ? ? ? ? ? ? ? ? ps 1.5 +67 +21 +67 +21 +67 +21 +79 +33 ? ? ? ? ? ? ? ? ? ? ps 1.0 0 0 0 0 0 0 +12 +12 +24 +24 ? ? ? ? ? ? ? ? ps 0.9 ? ? ?5 ?14 ?5 ? 14 +7 ? 2 +19 +10 +31 +22 ? ? ? ? ? ? ps 0.8 ? ? ? ? ?13 ?31 ?1 ? 19 +11 ? 7 +23 +5 +35 +17 ? ? ? ? ps 0.7 ? ? ? ? ? ? ?10 ? 42 +2 ? 30 +14 ? 18 +26 ? 6 +38 +6 ? ? ps 0.6 ? ? ? ? ? ? ? ? ?10 ? 59 +2 ? 47 +14 ? 35 +26 ? 23 +38 ? 11 ps 0.5 ? ? ? ? ? ? ? ? ? ? ?24 ?89 ?12 ? 77 0 ? 65 +12 ? 53 ps dq slew rate (v/ns) 0.4 ? ? ? ? ? ? ? ? ? ? ? ? ?52 ?140 ?40 ?128 ?28 ? 116 ps
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 22 [derating values of tis/tih (ddr2-667, 800)] ck, /ck differential slew rate 2.0 v/ns 1.5 v/ns 1.0 v/ns ? tis ? tih ? tis ? tih ? tis ? tih unit notes 4.0 +150 +94 +180 +124 +210 +154 ps 3.5 +143 +89 +173 +119 +203 +149 ps 3.0 +133 +83 +163 +113 +193 +143 ps 2.5 +120 +75 +150 +105 +180 +135 ps 2.0 +100 +45 +130 +75 +160 +105 ps 1.5 +67 +21 +97 +51 +127 +81 ps 1.0 0 0 +30 +30 +60 +60 ps 0.9 ?5 ? 14 +25 +16 +55 +46 ps 0.8 ?13 ? 31 +17 ? 1 +47 +29 ps 0.7 ?22 ? 54 +8 ? 24 +38 +6 ps 0.6 ?34 ?83 ?4 ? 53 +26 ? 23 ps 0.5 ?60 ?125 ?30 ? 95 0 ? 65 ps 0.4 ?100 ?188 ?70 ?158 ?40 ? 128 ps 0.3 ?168 ?292 ?138 ?262 ?108 ? 232 ps 0.25 ?200 ?375 ?170 ?345 ?140 ? 315 ps 0.2 ?325 ?500 ?295 ?470 ?265 ? 440 ps 0.15 ?517 ?708 ?487 ?678 ?457 ? 648 ps command/address slew rate (v/ns) 0.1 ?1000 ?1125 ?970 ?1095 ?940 ? 1065 ps
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 23 vdd tds tis tdh tih tds tis tdh tih tds1 tdh1 tds1 tdh1 vddq vih (ac) min. vih (dc) min. vref (dc) vil (dc) max. vil (ac) max. vss dqs dqs ck /dqs /ck vref to ac region vref to ac region dc to vref region dc to vref region nominal slew rate nominal slew rate ? tfs ? trh ? tfh ? trs vss vih (ac) min. vih (dc) min. vil (dc) max. vil (ac) max. vref (dc) vref (dc) - vil (ac) max. ? tfs setup slew rate falling signal vref (dc) - vil (dc) max. ? trh hold slew rate rising signal = = vih (ac) min. - vref (dc) ? trs setup slew rate rising signal vih (dc) min. - vref (dc) ? tfh hold slew rate falling signal = = single-ended dqs differential dqs, /dqs ck, /ck slew rate definition nominal
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 24 vdd tds tis tdh tih tds tis tdh tih tds1 tdh1 tds1 tdh1 vref (dc) vddq vih (ac) min. vih (dc) min. vref (dc) vil (dc) max. vil (ac) max. vss dqs single-ended dqs differential dqs, /dqs ck, /ck dqs ck /dqs /ck vih (ac) min. vih (dc) min. vil (dc) max. vil (ac) max. vss vref to ac region vref to ac region dc to vref region dc to vref region nominal line nominal line nominal line nominal line tangent line tangent line ? tfs ? trh ? tfh ? trs tangent line [vref (dc) - vil (ac) max.] ? tfs setup slew rate falling signal tangent line [vref (dc) - vil (dc) max.] ? trh hold slew rate rising signal = = tangent line [vih (ac) min. - vref (dc)] ? trs setup slew rate rising signal tangent line [vih (dc) min. - vref (dc)] ? tfh hold slew rate falling signal = = slew rate definition tangent
block diagram bank 7 bank 6 bank 5 bank 4 address, ba0, ba1, ba2 /cs /ras /cas /we command decoder input & output buffer latch circuit data control circuit column decoder row decoder memory cell array bank 0 sense amp. bank 1 bank 2 bank 3 control logic column address buffer and burst counter row address buffer and refresh counter mode register clock generator dq ck /ck cke dqs, /dqs dm dll ck, /ck odt rdqs, /rdqs
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 26 pin function ck, /ck (input pins) ck and /ck are differentia l clock inputs. all address and c ontrol input signals are sam pled on the crossing of the positive edge of ck and negative edge of /ck. output (read) d ata is re ferenced to th e crossings of ck and /ck (both directions of crossing). /cs (input pin) all commands are masked when /cs is re gistered high. / cs provides for external rank selection on s ystems with multiple ranks. /cs is considered part of the command code. /ras, /cas, /we (input pins) /ras, /cas and /we (along with /cs) define the command being entered. a0 to a13 (input pins) provided the ro w address for active commands an d t he column a ddress and auto prechar ge bit for read/w rite commands to select one location out of the memory array in the respective bank. the address inputs also provide the op-code during mode register set commands. [address pins table] address (a0 to a13) part number row address column address note p3r1ge3jgf ax0 to ax13 ay0 to ay9 P3R1GE4JGF ax0 to ax13 ay0 to ay9 1 note: 1. a13 pin is nc for 16 organization. a10 (ap) (input pin) a10 is sampled during a precharge command to determine whether the precharge applies to one ba nk (a10 = low) or all banks (a10 = high). if only one bank is to be prechar ged, the bank is selected by ba0, ba1 and ba2. ba0, ba1, ba2 (input pins) ba0, ba1 and ba2 define to which bank a n active, read, write or prech arge command is being appl ied. ba0 and ba1 also determine if the mode register or extended mode register is to be accessed during a mrs or emrs (1), emrs (2) cycle. [bank select signal table] ba0 ba1 ba2 bank 0 l l l bank 1 h l l bank 2 l h l bank 3 h h l bank 4 l l h bank 5 h l h bank 6 l h h bank 7 h h h remark: h: vih. l: vil.
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 27 cke (input pin) cke high acti vates, and cke lo w deactivates, internal cl ock signals a nd device in put buffers and output drivers. taking cke lo w provides precharge power-down and self-refr esh operation (all banks idle), or active power-down (row active in any bank). cke is s ynchronous for p ower down entry and exit, and for self-refresh e ntry. cke is asynchronous for self-refresh exit. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, /ck and cke are disabled during power-down. input buffers, excluding cke, are disabled during self- refresh. dm, udm and ldm (input pins) dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is samp led on both edge s of dqs. althou gh dm pins are i nput only, the dm loading matches the dq and dqs loading. for 8 configuration, dm function will be disabled when rdqs function is enabled by emrs. in 16 configuration, udm contro ls upper byte (dq8 to dq15) and l dm contro ls lower byte (dq0 to dq7). in this datasheet, dm represents udm and ldm. dq (input/output pins) bi-directional data bus. dqs, /dqs udqs, /udqs, ldqs, /ldqs (input/output pins) output with read data, inp ut with write data for source synchronous operation. edge-aligned with read data , centered in write data. used to capture wr ite data. /dqs can be disabled by emrs. in 16 configuration, udqs, /udqs control upper byte (dq8 to dq15) a nd ldqs, /ldqs control lower byte (dq0 to dq7). in this datasheet, dqs represents udqs and ldqs, /dqs represents /udqs and /ldqs. rdqs, /rdqs (output pins) differential data strobe for read oper ation only. dm a nd rdqs functions are s witch able by emrs. these pins exist only in 8 configuration. /rdqs out put will be disabled when /dqs is disabled by emrs . odt (input pins) odt (on die termination control) is a registered high signal that e nables termination resistance internal to the ddr2 sdram. when enabled, odt is only applied to ea ch dq, dqs, /dqs, rdqs, /rdqs, and dm signal for 8 configurations. for 16 configuration, odt is applied to each dq, udqs, /udqs, ldqs, /ldqs, u dm, and ldm signal. the odt pin will be ignor ed if the exte nded mode register (emrs) is programmed to disa ble odt. any time the emrs enabl es the odt function; odt may not be driven high until eight clocks after the emrs has been enabled. vdd, vss, vddq, vssq (power supply) vdd and vss are po wer supply pins for i nternal circuits . vddq and v ssq are po wer supply pins for the out put buffers. vddl and vssdl (power supply) vddl and vssdl are power supply pins for dll circuits. vref (power supply) sstl_18 reference voltage: (0.50 0.01) vddq
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 28 command operation command truth table the ddr2 sdram recognizes the following commands spec ified by the /cs, /ras, /cas, /we and address pins. cke function symbol previous cycle current cycle /cs /ras /cas /we ba0 ba1 ba2 a13 to a11 a10 a0 to a9 notes mode register set mrs h h l l l l l l l mrs opcode 1 extended mode register set (1) emrs(1) h h l l l l h l l emrs (1) opcode 1 extended mode register set (2) emrs(2) h h l l l l l h l emrs (2) opcode 1 auto-refresh ref h h l l l h 1 self-refresh entry self h l l l l h 1 self-refresh exit selfx l h h 1, 6 l h l h h h single bank precharge pre h h l l h l ba l 1, 2 precharge all banks pall h h l l h l h 1 bank activate act h h l l h h ba ra 1, 2, 7 write writ h h l h l l ba ca l ca 1, 2, 3 write with auto precharge writa h h l h l l ba ca h ca 1, 2, 3 read read h h l h l h ba ca l ca 1, 2, 3 read with auto precharge reada h h l h l h ba ca h ca 1, 2, 3 no operation nop h l h h h 1 device deselect desl h h 1 power-down mode entry pden h l h 1, 4 h l l h h h power-down mode exit pdex l h h 1, 4 l h l h h h remark: h : vih. l : vil. : vih or vil. ba : bank address. ra : row address. ca : column address. notes: 1. all ddr2 commands are defined by states of /c s, /ras, /cas, /w e and cke at the ri sing edge of the clock. 2. bank select (ba0, ba1 and ba2), det ermine which bank is to be operated upon. 3. burst reads or writes should not be terminated other than specifie d as reads interrupted by a read in burst read command [read] or writes interrupted by a write in burst write command [writ]. 4. the power-down mode does not perform any refresh operations. the duration of power-down is therefore limited by the refresh requirements of the device. one clock delay is required for mode entry and exit. 5. the state of odt does not affect the states describe d in this table. the odt function is not availa ble during self-refresh. 6. self-refresh exit is asynchronous. 7. 8-bank device sequential bank ac tivation restriction: no more than 4 ban ks may be activated in a rolli ng tfaw window. converting to clocks is done by dividi ng tfaw (ns) b y tck (ns) and rou nding up to ne xt integer value. as an example of the rolling window, if (tfaw/tck) rounds up to 10 clocks, and an activate command is issued in clock n, no more than three furt her activate commands may be issued in clock n+1 through n+9.
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 29 cke truth table cke current state* 2 previous cycle (n-1)* 1 current cycle (n) *1 command(n) *3 /cs, /ras, /cas, /we operation (n) *3 notes power-down l l maintain power-down 11, 13, 14 l h desl or nop power-down exit 4, 8, 11, 13 self-refresh l l maintain self-refresh 11, 14 l h desl or nop self-refresh exit 4, 5, 9 bank active h l desl or nop active power-down entry 4, 8, 10, 11, 13 all banks idle h l desl or nop precharge power-down entry 4, 8, 10, 11, 13 h l self self-refresh entry 6, 9, 11, 13 any state other than listed above h h refer to the command truth table 7 remark: h : vih. l : vil. : dont care. notes: 1. cke (n) is the logic st ate of cke at clock ed ge n; cke (n ? 1) was the state of cke at th e previous clock edge. 2. current state is the st ate of the ddr sdram immediat ely prior to clock edge n. 3. command (n) is the command registered at clock edge n, and operation (n) is a result of command (n). 4. all states a nd sequences not sh own are illegal or r eserved unless explicitly described elsewhere in t his document. 5. on self-refresh exit, [desl] or [nop] commands must be issued on every clock edge occurring during the txsnr period. read commands may be issued only after txsrd (200 clocks) is satisfied. 6. self-refresh mode can only be enter ed from the all banks idle state. 7. must be a legal command as def ined in the command truth table. 8. valid commands for power-down entry and exit are [nop] and [desl] only. 9. valid commands for self-refresh exit are [nop] and [desl] only. 10. power-down and self-refresh can not be entered while read or write operations, (extended) mode register set operations or prech arge operations are in pr ogress. see secti on power-down and self-refresh command for a detailed list of restrictions. 11. minimum cke high time is 3 clocks; minimum cke low time is 3 clocks. 12. the state of odt does not affect the states describe d in this t able. the odt function is not availa ble during self-refresh. see sect ion odt (on die termination). 13. the power-down does not perform any refresh oper ations. the duration of po wer-down mode is therefore limited by the refresh requirements outlined in section automatic refresh command. 14. means dont car e (including floating around vref) in self-refresh and power-down. however odt must be drive n high or lo w in power-down if the odt function is en abled (bit a2 or a6 set to 1 in emrs(1)).
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 30 function truth table the following tables s how the operations that are p erf ormed when each command is issued i n each state of the ddr2 sdram. current state /cs /ras /cas /we address command operation notes idle h desl nop l h h h nop nop l h l h ba, ca, a10 (ap) read/reada illegal 1 l h l l ba, ca, a10 (ap) writ/writa illegal 1 l l h h ba, ra act row activating l l h l ba pre nop l l h l a10 (ap) pall nop l l l h ref auto-refresh 2 l l l h self self-refresh 2 l l l l ba, mrs-opcode mrs mode register accessing 2 l l l l ba, emrs-opcode emrs (1) (2) extended mode register accessing 2 bank(s) active h desl nop l h h h nop nop l h l h ba, ca, a10 (ap) read/reada begin read l h l l ba, ca, a10 (ap) writ/writa begin write l l h h ba, ra act illegal 1 l l h l ba pre precharge l l h l a10 (ap) pall precharge all banks l l l h ref illegal l l l h self illegal l l l l ba, mrs-opcode mrs illegal l l l l ba, emrs-opcode emrs (1) (2) illegal read h desl continue burst to end -> row active l h h h nop continue burst to end -> row active l h l h ba, ca, a10 (ap) read/reada burst interrupt 1, 4 l h l l ba, ca, a10 (ap) writ/writa illegal 1 l l h h ba, ra act illegal 1 l l h l ba pre illegal 1, 8 l l h l a10 (ap) pall illegal 8 l l l h ref illegal l l l h self illegal l l l l ba, mrs-opcode mrs illegal l l l l ba, emrs-opcode emrs (1) (2) illegal
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 31 current state /cs /ras /cas /we address command operation notes write h desl continue burst to end -> write recovering l h h h nop continue burst to end -> write recovering l h l h ba, ca, a10 (ap) read/reada illegal 1 l h l l ba, ca, a10 (ap) writ/writa burst interrupt 1, 4 l l h h ba, ra act illegal 1 l l h l ba pre illegal 1, 8 l l h l a10 (ap) pall illegal 8 l l l h ref illegal l l l h self illegal l l l l ba, mrs-opcode mrs illegal l l l l ba, emrs-opcode emrs (1) (2) illegal read with auto precharge h desl continue burst to end -> precharging l h h h nop continue burst to end -> precharging l h l h ba, ca, a10 (ap) read/reada illegal 1, 7 l h l l ba, ca, a10 (ap) writ/writa illegal 1, 7 l l h h ba, ra act illegal 1, 7 l l h l ba pre illegal 1, 7, 8 l l h l a10 (ap) pall illegal 7, 8 l l l h ref illegal l l l h self illegal l l l l ba, mrs-opcode mrs illegal l l l l ba, emrs-opcode emrs (1) (2) illegal write with auto precharge h desl continue burst to end ->write recovering with auto precharge l h h h nop continue burst to end ->write recovering with auto precharge l h l h ba, ca, a10 (ap) read/reada illegal 1, 7 l h l l ba, ca, a10 (ap) writ/writa illegal 1, 7 l l h h ba, ra act illegal 1, 7 l l h l ba pre illegal 1, 7, 8 l l h l a10 (ap) pall illegal 7, 8 l l l h ref illegal l l l h self illegal l l l l ba, mrs-opcode mrs illegal l l l l ba, emrs-opcode emrs (1) (2) illegal
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 32 current state /cs /ras /cas /we address command operation notes precharging h desl nop -> enter idle after trp l h h h nop nop -> enter idle after trp l h l h ba, ca, a10 (ap) read/reada illegal 1 l h l l ba, ca, a10 (ap) writ/writa illegal 1 l l h h ba, ra act illegal 1 l l h l ba pre nop -> enter idle after trp l l h l a10 (ap) pall nop -> enter idle after trp l l l h ref illegal l l l h self illegal l l l l ba, mrs-opcode mrs illegal l l l l ba, emrs-opcode emrs (1) (2) illegal row activating h desl nop -> enter bank active after trcd l h h h nop nop -> enter bank active after trcd l h l h ba, ca, a10 (ap) read/reada illegal 1, 5 l h l l ba, ca, a10 (ap) writ/writa illegal 1, 5 l l h h ba, ra act illegal 1 l l h l ba pre illegal l l h l a10 (ap) pall illegal l l l h ref illegal l l l h self illegal l l l l ba, mrs-opcode mrs illegal l l l l ba, emrs-opcode emrs (1) (2) illegal write recovering h desl nop -> enter bank active after twr l h h h nop nop -> enter bank active after twr l h l h ba, ca, a10 (ap) read/reada illegal 1, 6 l h l l ba, ca, a10 (ap) writ/writa new write l l h h ba, ra act illegal 1 l l h l ba pre illegal 1 l l h l a10 (ap) pall illegal l l l h ref illegal l l l h self illegal l l l l ba, mrs-opcode mrs illegal l l l l ba, emrs-opcode emrs (1) (2) illegal
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 33 current state /cs /ras /cas /we address command operation notes write recovering with auto precharge h desl nop -> precharging after twr l h h h nop nop -> precharging after twr l h l h ba, ca, a10 (ap) read/reada illegal 1 l h l l ba, ca, a10 (ap) writ/writa illegal 1 l l h h ba, ra act illegal 1 l l h l ba pre illegal 1 l l h l a10 (ap) pall illegal l l l h ref illegal l l l h self illegal l l l l ba, mrs-opcode mrs illegal l l l l ba, emrs-opcode emrs (1) (2) illegal refresh h desl nop -> enter idle after trfc l h h h nop nop -> enter idle after trfc l h l h ba, ca, a10 (ap) read/reada illegal l h l l ba, ca, a10 (ap) writ/writa illegal l l h h ba, ra act illegal l l h l ba pre illegal l l h l a10 (ap) pall illegal l l l h ref illegal l l l h self illegal l l l l ba, mrs-opcode mrs illegal l l l l ba, emrs-opcode emrs (1) (2) illegal mode register accessing h desl nop -> enter idle after tmrd l h h h nop nop -> enter idle after tmrd l h l h ba, ca, a10 (ap) read/reada illegal l h l l ba, ca, a10 (ap) writ/writa illegal l l h h ba, ra act illegal l l h l ba pre illegal l l h l a10 (ap) pall illegal l l l h ref illegal l l l h self illegal l l l l ba, mrs-opcode mrs illegal l l l l ba, emrs-opcode emrs (1) (2) illegal
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 34 current state /cs /ras /cas /we address command operation notes extended mode h desl nop -> enter idle after tmrd register accessing l h h h nop nop -> enter idle after tmrd l h l h ba, ca, a10 (ap) read/reada illegal l h l l ba, ca, a10 (ap) writ/writa illegal l l h h ba, ra act illegal l l h l ba pre illegal l l h l a10 (ap) pall illegal l l l h ref illegal l l l h self illegal l l l l ba, mrs-opcode mrs illegal l l l l ba, emrs-opcode emrs (1) (2) illegal remark: h : vih. l : vil. : vih or vil. notes: 1. this command may be issued for other banks, depending on the state of the banks. 2. all banks must be in "idle". 3. all ac timing specs must be met. 4. only allowed at the boundary of 4 bits burst. burst interruptions at other timings are illegal. 5. available in case trcd is satisfied by al setting. 6. available in case twtr is satisfied. 7. the ddr2 s dram supports the conc urrent auto- precharge feature, a re ad with auto-precharge enabled,or a write with auto-precharge enabled, may be followed by any column command to other banks, as l ong as that command d oes not interrupt t he read or write data transfer, and all other re lated limitations apply. (e.g. conflict between read data and write data must be avoided.) the minimum delay from a read or write command with auto precharge enabled, to a command to a different bank, is summarized below. from command to command (different bank, non- interrupting command) minimum delay (concurrent ap supported) units read w/ap read or read w/ap bl/2 tck write or write w/ap (bl/2) + 2 tck precharge or activate 1 tck write w/ap read or read w/ap (cl ? 1) + (bl/2) + twtr tck write or write w/ap bl/2 tck precharge or activate 1 tck
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 35 8. the minimum delay from the read, write and precharge command to the precharge command to the same bank is summarized below. [precharge and auto precharge clarification] from command to command minimum delay between from command to to command units notes read precharge (to same bank as read) al + (bl/2) + max.(rtp, 2) ? 2 tck a, b precharge all al + (bl/2) + max.(rtp, 2) ? 2 tck a, b read w/ap precharge (to same bank as read w/ap) al + (bl/2) + max.(rtp, 2) ? 2 tck a, b precharge all al + (bl/2) + max.(rtp, 2) ? 2 tck a, b write precharge (to same bank as write) wl + (bl/2) + twr tck b precharge all wl + (bl/2) + twr tck b write w/ap precharge (to same bank as write w/ap) wl + (bl/2) + wr tck b precharge all wl + (bl/2) + wr tck b precharge precharge (to same bank as precharge) 1 tck b precharge all 1 tck b precharge all precharge 1 tck b precharge all 1 tck b a. rtp[cycles] = ru{ trtp[ns] / tck[ns] }, where ru stands for round up. tck(avg) should be used in place of tck for ddr2-667/800. b. for a given bank, the precharge period should be coun ted from the latest prec harge command, either one bank precharge or prec harge all, issued to that ba nk. the precharge period is sati sfied after tr p depending on the latest prechar ge command issued to that bank.
simplified state diagram act cke_h cke_l pre (e)mrs cke_h cke_l cke_l cke_l cke_l cke_h cke_l cke_l read read read writ writ writ reada reada reada writa writa writa self ref initialization sequence auto refresh idle all banks precharged precharge power down bank active activating active power down write writa precharge pre, pall pre, pall pre, pall reada read mrs emrs (1) emrs (2) emrs (3) automatic sequence command sequence self refresh simplified state diagram
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 37 operation of ddr2 sdram read and write accesses to the ddr2 sdram are burst orient ed; accesses start at a selected location and continue for the fixed burst length of four or eight in a programme d sequence. accesses begin with the regi stration of an active command, which is then follo wed by a read or writ e command. the address bits registered co incident with the active command is used to select the bank and ro w to be accessed ba0, ba1 and ba2 select the bank; a0 to a13 select the row). the address bits registered coi ncident with the read or write command are used to select th e starting column location for the burst access and to det ermine if the auto precharge command is to be issued. prior to normal operation, the ddr2 sdram must be initialized. the following sections provide detailed information covering device initialization; register defini tion, command descriptions and device operation. power on and initialization ddr2 sdrams must be po wered up and initialized in a pr edefined manner. operati onal procedures other than those specified may result in undefined operation. power-up and initialization sequence the following sequence is required for power up and initialization. 1. apply power and attempt to maintain cke below 0.2 vddq and odt * 1 at a low state (all other inputs may be undefined.) ? vdd, vddl and vddq are driven from a single power converter output, and ? vtt is limited to 0.95v max, and ? vref tracks vddq/2. or ? apply vdd before or at the same time as vddl. ? apply vddl before or at the same time as vddq. ? apply vddq before or at the same time as vtt and vref. at least one of these two sets of conditions must be met. 2. start clock and maintain stable condition. 3. for the minimum of 200 s after stable po wer and clock ( ck, /ck), then apply [nop] o r [desl] and take cke high. 4. wait minimum of 400ns then issue precharge all co mmand. [nop] or [desl] applied during 400ns period. 5. issue emrs (2) command. (to issue emrs (2) command, provide low to ba0 and ba2, high to ba1) 6. issue emrs (3) command. (to issue emrs (3) command, provide low to ba2, high to ba0 and ba1) 7. issue emrs to ena ble dll. (to issue dll ena ble co mmand, provide low to a0, hi gh to ba0 and l ow to ba1, ba2 and a13.) 8. issue a mode register set command for dll reset. (to issue dll reset command, provide high to a8 and low to ba0 to ba2 and a13) 9. issue precharge all command. 10. issue 2 or more auto-refresh commands. 11. issue a mode register set command with low to a8 to initialize device operation. (i.e. to program oper ating parameters without resetting the dll.) 12. at least 200 clocks after ste p 8, issue emrs (1) co mmand with a9 = a8 = a7 = 1. then issue emrs (1) command with a9 = a8 = a7 = 0 with ot her operating parameters of emrs (1). 13. the ddr2 sdram is now ready for normal operation. note: 1. to guarantee odt off, vref must be valid and a low level must be ap plied to the odt pin. emrs(3) mrs tmrd tmrd tmrd 200 cycles (min) tmrd tmrd trp trfc trfc pall mrs ref ref emrs(1) emrs(1) dll enable dll reset any command emrs(2) command pall trp 400ns nop ck /ck cke tch tcl tis a9=a8=a7=1 a9=a8=a7=0 emrs(1) power up and initialization sequence
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 38 programming the mode register and extended mode registers for application flexibility, burst length, burs t type, /cas la tency, dll r eset function, w rite recovery time (tw r) are user defin ed variables and must be pr ogrammed with a mode reg ister set command [mrs]. addition ally, dll disable function, driver im pedance, additive /cas latenc y, odt (on die t ermination) and single-ended strobe ar e also user defined variables and must be programmed wi th an extended mode register set com mand [emrs]. contents of the mode re gister (mr) or extended mode registers (em rs (#)) can b e altered by reexecuting the mrs and emrs commands. if the user chooses to m odify only a subset of th e mrs or emr s variables, all variables must be redefined when the mrs or emrs commands are issued. mrs, emrs and reset dll do not affect arra y contents , which means reinitialization including those can be executed any time after power-up without affecting array contents. ddr2 sdram mode register set [mrs] the mode re gister stores the data for c ontrolling the vari ous operating modes of ddr2 sdram. it c ontrols /cas latency, burst length, burst sequence, dll reset, twr and various vendor specific options to make d dr2 sdram useful for vario us applications. the default value of the mo de register is not defined, therefore the mo de register must be written after po wer-up for proper operation. the mode register is written by asserting low on /cs, /ras, /cas, /we, ba0, ba1 and ba2, while control ling the state of address pins a0 to a13. the ddr2 sdram should b e in all bank p recharge with cke already high prior to writing into the mode reg ister. the mode register set command cycle time (tmrd) is requir ed to complete the write operation to the mode reg ister. the mode register contents can be c hanged using the same command an d clock cycle requirements during normal operation as long as all banks are in the precharge state. the mode register is divided into various fields depending on functionality. burst le ngth is defin ed by a0 to a2 with options of 4 a nd 8 bit burst lengths. t he burst len gth decodes are compatible with ddr sdram. burst address s equence type is defined b y a3, /cas latency is defined by a4 to a6. the ddr2 doesnt supp ort half clock latenc y mode. a8 is used for dll reset. write recovery time twr is defined by a9 to a11. refer to the table for specific codes. notes: 1. a13 is reserved for future use and must be programmed to 0 when setting the mode register. 2. wr (min.) (write recovery for autoprecharge) is determined by tck (max.) and wr (max.) is determined by tck (min.). wr in clock cycles is calculated by dividing twr (in ns) by tck (in ns) and rounding up to the next integer (wr [cycles] = twr (ns) / tck (ns)). the mode register must be programmed to this value. this is also used with trp to determine tdal. 0pd ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 00 * 1 ba1 ba2 wr a8 0 1 dll reset no ye s dll 0 /cas latency bt burst length mode register a6 0 0 0 0 1 1 1 1 /cas latency a5 0 0 1 1 0 0 1 1 a4 0 1 0 1 0 1 0 1 latency reserved reserved reserved 3 4 5 6 reserved a3 0 1 burst type sequential interleave a12 0 1 active power down exit timing fast exit (use txard timing) slow exit (use txards timing) a2 0 0 burst length a1 1 1 a0 0 1 bl 4 8 a11 0 0 0 0 1 1 1 1 write recovery for autoprecharge a10 0 0 1 1 0 0 1 1 a9 0 1 0 1 0 1 0 1 wr reserved 2 3 4 5 6 reserved reserved ddr2-400 ddr2-533 ddr2-667 ddr2-800 ba1 0 0 1 1 mrs mode mrs emrs(1) emrs(2) emrs(3): reserved ba0 0 1 0 1 ba2 0 0 0 0 mode register set (mrs)
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 39 ddr2 sdram extended mode registers set [emrs] emrs (1) programming the extended mode register (1) stores the data for e nabling or disabling the dll, output driver stre ngth, additive latency, odt, /dqs disable, rdqs enabl e. the default value of the exten ded mode register (1) is not defined, therefore the extended mode register (1) mu st be writte n after power-up for proper operation. the extended mode register (1) is written by asserting low on /cs, /ras, /c as, /we, high on ba0 and low on ba1, ba2 while controlling the states of a ddress pins a0 to a 13. t he ddr2 sdram should be in all bank precharge with cke already high prior to writing into the exte nded mode register (1). the mode register set command cycle time (tmrd) must be satisfied to complete the write operation to the extended mode register (1). mode regi ster contents can be changed using the s ame command and clock cycle requirements dur ing normal operation as long as all banks are i n the precharge state. a0 is used for dll enab le or disab le. a1 is used for setti ng output driver str ength. a3 to a5 determines the additive latency. a10 is used for /dqs enabl e or disable. a11 is used for rdqs enable. a2 and a6 are used for odt setting. notes: 1. a13 are reserved for future use, and must be programmed to 0 when setting the extended mode register. 2. it must be set to 1 first, and then set to 0 in initialization. refer to the power-up and initialization sequence for detailed information. 3. output disabled - dq, dqs, /dqs, rdqs, /rdqs. this feature is used in conjunction with dimm idd measurements when iddq is not desired to be included. a13 ba0 ba1 ba2 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field a11 0 1 rdqs enable disable enable 1 0 0 0* /dqs 0 * 2 rtt additive latency rtt d.i.c dll extended mode register a10 0 1 /dqs enable enable disable a5 0 0 0 0 1 1 1 1 additive latency a4 0 0 1 1 0 0 1 1 a3 0 1 0 1 0 1 0 1 latency 0 1 2 3 4 5 reserved reserved a0 0 1 dll enable enable disable ba1 0 0 1 1 ba2 0 0 0 0 mrs mode mrs emrs(1) emrs(2) emrs(3): reserved a6 0 0 1 1 a2 0 1 0 1 rtt (nominal ) odt disabled 75? 150? 50? a1 0 1 driver strength control output driver impedance control normal weak driver size 100% 60% 1 rdqs qoff ba0 0 1 0 1 a11 (rdqs enable) 0 (disable) 0 (disable) 1 (enable) 1 (enable) a10 (/dqs enable) 0 (enable) 1 (disable) 0 (enable) 1 (disable) rdqs/dm dm dm rdqs rdqs /rdqs high-z high-z /rdqs high-z dqs dqs dqs dqs dqs /dqs /dqs high-z /dqs high-z strobe function matrix a12 0 1 qoff* output buffers enabled output buffers disabled 3 emrs (1)
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 40 dll enable/disable the dll must be ena bled for normal op eration. dll en able is re quired during power up initia lization, and u pon returning to normal operation after having the dll disabled. the dll is automatically disabled when entering self- refresh operation and is automatically re-enabled upon exit of self-refresh oper ation. an y time the dll is enabled (and subsequently reset), 200 clock cycles must occur before a read co mmand can be issued to allo w time for the internal clock to be synchronized with the external clock. failing to wait for synchronization to occur may result in a violation of the tac or tdqsck parameters. emrs (2) programming *1 the extended mode register (2) controls refresh related fe atures. the de fault value of the extended mode register (2) is not defined, therefore the extended mode register (2) must be written after power-up for proper operation. the extended mode register (2) is written by asserting lo w on cs, /ras, /cas, /w e, high on ba1 and low on ba0, ba2 while controlling the states of address pins a0 to a13. the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode regist er (2). the mode register set command c ycle time (tmrd) must be satisfied to complete the write operation to the extended mode register (2). mo de register contents can be changed using the same command and clock cycle requirement s during normal operation as long as all banks are in the precharge state. a7 is used for high te mperature self-refresh rate enable or disable. address field a13 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba1ba2 ba0 a12 0* 1 extended mode register (2) 0* 1 0* srf 1 01 a7 0 1 high temperature self-refresh rate enable disable enable note: 1. the rest bits in emrs (2) is reserved for future use and all bits in emrs (2) except a7 must be programmed to 0 when setting the extended mode register (2) during initialization. emrs (2) emrs (3) programming: reserved *1 extended mode register(3) 0* 1 110 address field a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba1ba2 ba0 a12 a13 note : 1. emrs (3) is reserved for future use and all bits must be programmed to 0 when setting the extended mode register (3) during initialization. emrs (3)
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 41 odt (on die termination) on die termination (odt), is a feature that allows a dram to turn on/off te rmination resistance for each dq, dqs, /dqs rdqs, /rdqs, and dm signal via the odt control pin. the odt feature is designed to improve sign al integrity of the memory channel by allowing the dram controller to inde pendently turn on/off termination resistance for any or all dram devices. the odt function is turned off and not supported in self-refresh mode. odt must be disabled externally during reads by driving odt low. switch sw1, sw2 or sw3 is enabled by odt pin. selection between sw1, sw2 or sw3 is determined by rtt (nominal) in emrs termination included on all dqs, dm, dqs, /dqs, rdqs and /rdqs pins. target rtt (?) = (rval1) / 2, (rval2) / 2 or (rval3) / 2 dram input buffer vddq vssq sw1 sw1 sw2 rval1 rval1 input pin vddq vssq sw2 rval2 rval2 sw3 vddq vssq sw3 rval3 rval3 functional representation of odt command emrs nop old setting tmod (min.) tmod (max.) taofd tis updating new setting ck /ck odt rtt note: taofd must be met before issuing emrs command. odt must remain low for the entire duration of tmod window. odt update delay timing
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 42 ck /ck t0 t1 t2 t3 t4 t5 t6 odt cke internal term res. rtt tis tis taond taofd taon max. taon min. taof min. taof max. odt timing for active and standby mode ck /ck t0 t1 t2 t3 t4 t5 t6 odt cke internal term res. rtt tis tis taonpd min. taonpd max. taofpd min. taofpd max. odt timing for power-down mode
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 43 t-5 t-4 t-3 t-2 t-1 t0 t1 t2 t3 t4 /ck ck cke odt internal term res. internal term res. internal term res. internal term res. tis tis tis odt tis odt odt tis active and standby mode timings to be applied. active and standby mode timings to be applied. power down mode timings to be applied. power down mode timings to be applied. rtt rtt rtt rtt taofpd(max.) taofd taond taonpd(max.) tanpd entering slow exit active power down mode or precharge power down mode. odt timing mode switch at entering power-down mode
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 44 t0 t1 t4 t5 t6 t7 /ck ck t8 cke odt internal term res. internal term res. internal term res. internal term res. tis tis tis t9 t10 t11 odt tis odt active and standby mode timings to be applied. active and standby mode timings to be applied. odt tis power down mode timings to be applied. power down mode timings to be applied. exiting from slow active power down mode or precharge power down mode. rtt rtt rtt rtt taxpd taofpd (max.) taonpd (max.) taofd taond odt timing mode switch at exiting power-down mode
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 45 bank activate command [act] the bank activate command is issued by holding /cas and /we high with /cs and /ras low at the rising edge of the clock. the bank addresses ba0, ba1 and ba2 are used to select the desired bank. the row address a0 through a13 is used to determin e which row to activate in t he selected bank. t he bank activate command must be applied before any read or write oper ation can be executed. immediately afte r the bank active command, the ddr2 sdram can accept a read or write command on the following clock cycle. if a r /w command is issued to a bank that has not satisfied the trcd (min.) specificat ion, then additive latency must be pr ogrammed into the device to delay when the r/w command is inter nally issued to the devic e. t he additive latency value must be chosen to assure trcd (min.) is satisfied. additive la tencie s of 0, 1, 2, 3 and 4 are supported. once a bank h as been activated it must be precharged before another bank activate c ommand can be applied to the same ba nk. the bank active an d precharge times are defined as tras and trp, respectively. the minimum time interval between successive bank activate commands to t he same bank is d etermined by t he /ras c ycle time of the device (trc), which is e qual to tras + trp. the minimum time interv al between successive bank activate commands to the different bank is determined by (trrd). in order to en sure that 8-ba nk devic es do not exc eed the instantaneous cu rrent supplying capability of 4-b ank devices, a restriction on the number of sequential act commands that can be issued must be observed. the rule is as follows: note: 8-bank device sequential bank activation restriction: no more than 4 banks may be activated in a rolli ng tfaw window. conv erting to clocks is done by dividing tfaw (ns) by tck (ns) a nd rounding up to nex t integer value. as an e xample of the ro lling window , if (tfaw/tck) rounds up to 10 clocks, and an activate command is is sued in clock n, no more th an three furth er activate com mands may be issued i n clock n+1 through n+9. /ck ck address command t0 t1 t2 t3 tn tn+1 tn+2 tn+3 trcd(min.) tras trp trc row: 0 act bank0 active bank1 active bank0 active bank0 precharge bank1 precharge posted read posted read act pre pre act col: 0 row: 0 row: 1 col: 1 tccd additive latency (al) trrd bank0 read begins bank activate command cycle (trcd = 3, al = 2, trp = 3, trrd = 2, tccd = 2)
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 46 read and write access modes after a bank has been activated, a read or write cycle can be executed. this is accomplished by setting /ras high, /cs and /cas low at the clocks rising edge. /we must also be defined at this time to determine whether the access cycle is a read operation (/we high) or a write operation (/we low). the ddr2 sdram provides a fast column access operation. a single read or write command will initiate a serial read or write operation on successive clock cycles. the boundar y of the burst cycle is strict ly restricted to specific segments of th e page le ngth. for example, the 32m bits 4 i/o 4 banks chip has a page len gth of 2048 bits (defined by ca0 to ca9, c a11). t he page length of 2048 is divided into 5 12 uniquely addressable boundary segments (4 bits each). a 4 bits bur st operation will occur entirely within one of the 512 groups beginning with the column address supplied to the device dur ing the read or write command (ca0 to ca9, ca11). the second, third and fourth access will also occur within this group s egment, however, the burst ord er is a function of the startin g address, and the burst sequence. a new burst access must not interrupt the previous 4-bit burst operation. the minimum /cas to /cas dela y is defined by tccd, and is a minimum of 2 clocks for read or write cycles. posted /cas posted /cas operation is supported to make command and data bus efficient for sustainable bandwidths in ddr2 sdram. in this operation, the ddr2 sdram allows a /cas read or write command to be issued imme diately after the /ras bank activate command (or any time during the /ras-/cas-delay time, trcd, period). t he command is held for the ti me of the add itive laten cy (al) before it i s issued i nside t he device. the read l atency (rl) is controlled by the sum of al and the /cas latency (cl). t herefore if a user chooses to issue a r/w command before the trcd (min), then al (greater than 0) must be written into the emrs. the write latency (wl) is always defined as rl ? 1 (read latency ? 1) where read latency is defined as the sum of additive latency plus /cas latency (rl = al + cl). -1 /ck ck dqs, /dqs al = 2 trcd trac cl = 3 command dq 0123456789101112 act read nop nop writ out0 out1 out2 out3 in0 in1 in2 in3 wl = rl ? 1 = 4 rl = al + cl = 5 read followed by a write to the same bank [al = 2 and cl = 3, rl = (al + cl) = 5, wl = (rl - 1) = 4] -10123456789101112 /ck dqs, /dqs al = 0 trcd trac cl = 3 command dq act read writ out0 out1 out2 out3 in0 in1 in2 in3 ck rl = al + cl = 3 wl = rl ? 1 = 2 nop nop nop read followed by a write to the same bank [al = 0 and cl = 3, rl = (al + cl) = 3, wl = (rl - 1) = 2]
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 47 burst mode operation burst mode operation is used to provide a constant flow of data to memor y locations (write cycle), or from memo ry locations (read cycle). the parameters that define how th e burst mod e will operate are burst seq uence and burst length. ddr 2 sdram su pports 4 bits burst and 8 bits burs t modes only. f or 8 bits burst mode, full interleave address ordering is supporte d, however, sequential address ordering is nibb le based for ease of implement ation. the burst type, either sequential or in terleaved, is programmable and defined by the address bit 3 (a3) of the mrs, which is similar to the ddr-i sdram operation. seam less burst read or write oper ations are supported. unlike ddr-i devices, interruption of a burst read or writes o peration is limited to ready by read or write by write at the boundary of burst 4. therefore the burst stop command is not supported on ddr2 sdram devices. [burst length and sequence, bl = 4] burst length starting address (a1, a0) sequential addressing (decimal) interl eave addressing (decimal) 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 4 11 3, 0, 1, 2 3, 2, 1, 0 [burst length and sequence, bl = 8] burst length starting address (a2, a1, a0) sequential addressing (decimal) interl eave addressing (decimal) 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 011 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 8 111 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 note: page length is a function of i/o organization and column addressing 16m bits 8 organization (ca0 to ca9); page length = 1024 bits 8m bits 16 organization (ca0 to ca9); page length = 1024 bits
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 48 burst read command [read] the burst read comman d is initiated by having /cs a nd /cas low while holding /ras and /we high at the risin g edge of the clock. the address inputs determine the starting column address for the burst. the delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read late ncy (rl). the data strobe outp ut (dqs) is driven lo w 1 clock cy cle before valid data (dq) is driven onto the data bus. the first bit of the burst is synchro nized with the risi ng edge of the data strobe (dqs). each subsequent data-out appears on the dq pin in phase with the dqs signal in a source synchronous manner. the rl is equal to an additiv e latency (al) plus /cas late ncy (cl). t he cl is defined by the mode register set (mrs), similar to the e xisting sdr and ddr-i sdrams. t he al is d efined by the extended mode register set (emrs). read nop /ck ck t0 t1 t2 t3 t4 t5 t6 t7 t8 command dqs, /dqs dq out0 out1 out2 out3 cl = 3 rl = 3 tdqsck burst read operation (rl = 3, bl = 4 (al = 0 and cl = 3)) read nop /ck ck t0 t1 t2 t3 t4 t5 t6 t7 t8 command dqs, /dqs dq out0 out1 out2 out3 out4 out5 out6 out7 tdqsck cl = 3 rl = 3 burst read operation (rl = 3, bl = 8 (al = 0 and cl = 3))
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 49 posted read nop ck /ck t0 t1 t2 t3 t4 t5 t6 t7 t8 command dqs, /dqs dq al = 2 cl = 3 rl = 5 out0 out1 out2 out3 tdqsck burst read operation (rl = 5, bl = 4 (al = 2, cl = 3)) posted read nop ck /ck t0 t1 t3 t4 t5 t6 t7 t8 t9 command dqs, /dqs dq nop posted writ rl = 5 out0 out1 out2 out3 in0 in2 nop in3 in1 trtw (read to write = 4 clocks) wl = rl - 1 = 4 burst read followed by burst write (rl = 5, wl = rl-1 = 4, bl = 4) the minimum time from the burst read co mmand to the burst write command is defi ned by a rea d-to-write-turn- around-time, which is 4 clocks in the case of bl = 4 operation, 6 clocks in case of bl =8 operation. posted read nop ck /ck t0 t1 t2 t3 t4 t5 t6 t7 t8 command dqs, /dqs dq posted read nop out a0 al = 2 ab cl = 3 rl = 5 out a1 out a2 out a3 out b0 out b1 out b2 seamless burst read operation (rl = 5, al = 2, and cl = 3)
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 50 enabling a read comman d at ever y other clock support s t he seamless burst read operat ion. this operation is allowed regardless of same or different banks as long as the banks are activated. read nop read /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 command dqs, /dqs dq nop rl = 4 burst interrupt is only allowed at this timing. out a0 out a1 out a2 out a3 out b0 out b1 out b2 out b3 out b4 out b5 out b6 out b7 a b burst read interrupt by read notes: 1. read burst interrupt function is only allowed on burst of 8. burst inte rrupt of 4 is prohibited. 2. read burst of 8 can o nly be in terrupted by another read command. r ead burst interruption by write command or precharge command is prohibited. 3. read burst interrupt must occur exactl y two clo cks after previous re ad command. an y other read b urst interrupt timings are prohibited. 4. read burst interruption is allowed to any bank inside dram. 5. read burst with auto precharge enabled is not allowed to interrupt. 6. read burst interruption is allowed by another read with auto precharge command. 7. all command timings are referenced to burst length set in the mod e register. they are not referenced to actual burst. for e xample, minimum read to prechar ge timing is al + bl/2 where bl is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt).
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 51 burst write command [writ] the burst write command is initiated by having /cs, /cas and /we low while holding /ras high at the rising edge of the clock. the address inputs determine the starting col umn address. w rite latency (w l) is define d by a re ad latency (rl) minus one and is equal to (al + cl ? 1). a data strobe si gnal (dqs) should be driven low (preamble) one clock prior to the wl. the first data bit of the burst c ycle must be applied to the dq pins at the first rising edge of the dqs follo wing the pr eamble. t he tdqss specific ation must be satisfied for write cycles. the subsequent burst bit data a re issued on successive edges of the dqs until the burst length of 4 is completed. when the burst has finished, any additional data supplied to the dq pi ns will be ignored. the dq signal is ignored after the burst write operation is complete. the time from the completion of the burst write to bank prec harge is the write recovery time (twr). writ nop ck /ck t0 t1 t2 t3 t4 t5 t6 t7 t9 command dqs, /dqs dq in2 pre nop act in1 in3 in0 wl = rl ?1 = 2 tdqss trp twr completion of the burst write burst write operation (rl = 3, wl = 2, bl = 4 twr = 2 (al=0, cl=3)) writ nop ck /ck t0 t1 t2 t3 t4 t5 t6 t7 t8 command dqs, /dqs dq trp twr in2 in1 in3 in0 in6 in5 in7 in4 wl = rl ?1 = 2 t9 t11 nop act pre tdqss completion of the burst write burst write operation (rl = 3, wl = 2, bl = 8 (al=0, cl=3))
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 52 posted writ nop ck /ck t0 t1 t2 t3 t4 t5 t6 t7 t9 command dqs, /dqs dq wl = rl ?1 = 4 twr in0 in1 in2 in3 pre tdqss completion of the burst write burst write operation (rl = 5, wl = 4, bl = 4 twr = 3 (al=2, cl=3)) nop ck /ck t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 command dqs, /dqs dq cl = 3 rl = 5 al = 2 >twtr in0 in2 nop in1 in3 posted read = wl = rl ?1 = 4 write to read = cl - 1 + bl/2 + twtr (2) = 6 out0 out1 burst write followed by burst read (rl = 5, bl = 4, wl = 4, twtr = 2 (al=2, cl=3)) the minimum number of clock from the bur st write command to the burst read command is cl - 1 + bl/2 + a write to-read-turn-around-time (twtr). this twtr is not a write recovery time (twr) but the ti me required to transfer the 4bit write data from the input buffer into sense amplifiers in the array. nop /ck ck t0 t1 t2 t3 t4 t5 t6 t7 t8 command dqs, /dqs dq in a0 in a2 nop in a1 in a3 in b0 in b2 in b1 in b3 posted writ posted writ wl = rl ? 1 = 4 ab seamless burst write operation (rl = 5, wl = 4, bl = 4) enabling a write command every other clock supports the seam less burst write operation. this operation is allowed regardless of same or different banks as long as the banks are activated.
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 53 writ nop writ /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 command dqs, /dqs dq nop burst interrupt is only allowed at this timing. in b7 a b wl = 3 in a0 in a1 in a2 in a3 in b0 in b1 in b2 in b3 in b4 in b5 in b6 write interrupt by write (wl = 3, bl = 8) notes :1. write burst interrupt function is only allowed on burst of 8. burst interrupt of 4 is prohibited. 2. write burst of 8 can o nly be interrupted by another write command. write burst int erruption by read command or precharge command is prohibited. 3. write burst interrupt must occur exactly two clo cks after previous write command. any other write burst interrupt timings are prohibited. 4. write burst interruption is allowed to any bank inside dram. 5. write burst with auto precharge enabled is not allowed to interrupt. 6. write burst interruption is allowed by another write with auto precharge command. 7. all command timings are referenced to burst length set in the mod e register. they are not referenced to actual burst. for example, minimum write to prec harge timing is w l+bl/2+twr where twr starts with the rising clock after the un-interrupted burst end and not from the end of actual burst end.
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 54 write data mask one write data mask (dm) pin for each 8 d ata bits (dq) w i ll be supported on ddr2 sdrams, consistent with the implementation on ddr-i sdrams. it has identical timings on wr ite operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. dm is not used during read cycles. dq dqs /dqs t1 t2 t3 t4 t5 tn dm write mask latency = 0 in in in in in in in in in data mask timing /ck ck dqs, /dqs dq dm dqs, /dqs dq dm command [tdqss(min.)] twr tdqss wl tdqss wl [tdqss(max.)] writ nop in0 in2 in3 in0 in2 in3 data mask function, wl = 3, al = 0 shown
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 55 precharge command [pre] the precharge command is used to prec harge or close a bank that has been ac tivated. the precharge command is triggered when /cs, /ras and /w e are l ow and /cas i s hi gh at the rising edge of the clock. t he precharge command can be used to pre charge each bank independently or all banks simultaneously. three address bits a10, ba0, ba1 and ba2 are used to define which bank to precharge when the command is issued. [bank selection for precharge by address bits] a10 ba0 ba1 ba2 precharged bank(s) l l l l bank 0 only l h l l bank 1 only l l h l bank 2 only l h h l bank 3 only l l l h bank 4 only l h l h bank 5 only l l h h bank 6 only l h h h bank 7 only h all banks 0 to 7 remark: h: vih. l: vil. : vih or vil. burst read operation followed by precharge minimum read to precharge command spacing to the same bank = al + bl/2 clocks for the earliest possible precharge, the precharge command may be issued on the rising edge that is additive latency (al) + bl/2 clocks after a read comm and. a ne w bank active (command) may be issued to the same bank after the ras precharge time (trp). a pr echarge command cannot be issued until tras is satisfied. nop ck /ck t0 t1 t2 t3 t4 t5 t6 t7 t8 command dqs, /dqs dq rl = 4 al = 1 cl = 3 out0 out2 pre nop out1 out3 posted read nop t rp t ras act al + bl/2 clocks burst read operation followed by precharge (rl = 4, bl = 4 (al=1, cl=3))
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 56 nop ck /ck t0 t1 t2 t3 t4 t5 t6 t7 t8 command dqs, /dqs dq rl = 5 al = 2 cl = 3 out0 out2 nop pre out1 out3 posted read act nop al + bl/2 clocks t rp t ras(min.) burst read operation followed by precharge (rl = 5, bl = 4 (al=2, cl=3)) nop ck /ck t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 command dqs, /dqs dq al = 2 cl = 4 out0 out2 nop pre out1 out3 out4 out6 out5 out7 posted read act nop t rp rl = 6 al + bl/2 clocks t ras(min.) burst read operation followed by precharge (rl = 6 (al=2, cl=4, bl=8))
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 57 burst write followed by precharge minimum write to precharge command spacing to the same bank = wl + bl/2 clocks + twr for write cycles, a del ay must be satisfi ed from the com ple tion of th e last burst write cycle until the precharge command can be issued. this delay is known as a write reco very time (twr) referenced from the completion of the burst write to the precharge command. no precharge command should be issued prior to the tw r delay, as ddr2 sdram allows the burst interrupt operation only read by read or write by write at the boundary of burst 4. in3 in1 nop ck /ck t0 t1 t2 t3 t4 t5 t6 t7 t8 command dqs, /dqs dq twr completion of the burst write wl = 3 in0 in2 posted writ pre burst write followed by precharge (wl = (rl-1) =3) posted writ ck /ck t0 t1 t2 t3 t4 t5 t6 t7 t9 command dqs, /dqs dq wl = 4 in0 in1 in2 in3 pre twr completion of the burst write nop burst write followed by precharge (wl = (rl-1) = 4)
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 58 posted writ nop ck /ck t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t11 command dqs, /dqs dq wl = 4 in0 in1 in2 in3 in4 in5 in6 in7 twr completion of the burst write pre burst write followed by precharge (wl = (rl-1) = 4,bl= 8)
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 59 auto precharge operation before a new row in an active bank can be opened, the ac tive bank must be precharged using either the precharge command or the auto precharge function. when a read or a write command is given to the ddr2 sdram, the /cas timing accepts one extra address, column address a10, to a llow the active bank to automat ically begin precharge at the earliest possible moment during the bu rst read or write cycle. if a10 is lo w when the read or write command is issued, then normal read or write burst operation is executed and the ba nk remains active at the completio n of the burst sequence. if a10 is high when the read or w rite command is issued, then the auto precharge function is engaged. during auto precharge, a read command will execut e as normal with the exception that the active bank will begin to precharge on the rising edge which is /cas late ncy (cl) clock cycles before the end of the read burst. auto precharge can also be implemented during write commands. the precharge operation engaged by the auto precharge command will not begi n until th e la st data of the burst wr ite sequence is pro perly stored i n the memor y array. this feature allows the prec harge operation to be partially or completely hidden during burst read cycles (dependent upon /cas latency) thus improving system performance for random data access. the /ras lockout circuit internally delays the precharge operation until the ar ray restore ope ration has b een completed so that the aut o precharge command may be issued with any read or write command. burst read with auto precharge [reada] if a10 is high w hen a r ead command is issued, the re ad with auto p recharge function is eng aged. the ddr2 sdram starts an auto precharge operation on the rising edge wh ich is (al + bl/2) cycles later from the read with ap command when tras ( min) is satisfie d. if tras (min.) is not sati sfied at the e dge, the start point of aut o precharge operation will be delayed until tras (min.) is sati sfied. a ne w bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously. (1) the /ras precharge time (trp) has been satisfied from the clock at which the auto precharge begins. (2) the /ras cycle time (trc) from the prev ious bank activation has been satisfied. nop nop ck /ck t0 t1 t2 t3 t4 t5 t6 t7 tn command dqs, /dqs dq auto precharge begins out0 out2 out1 out3 posted read act act al + bl/2 a10 = 1 trc (min.) cl = 3 al = 2 rl = 5 trp burst read with auto precharge followed by an activation to the same bank (trc limit) (rl = 5, bl = 4 (al = 2, cl = 3, trtp 2tck))
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 60 nop ck /ck t0 t-1 t1 t2 t3 t4 t5 t6 t7 tn command dqs, /dqs dq auto precharge begins out0 out2 out1 out3 posted read act trp tras(min.) a10 = 1 trc (min.) cl = 3 rl = 5 al = 2 burst read with auto precharge followed by an activation to the same bank (tras lockout case) (rl = 5, bl = 4 (al = 2, cl = 3)) nop ck /ck t0 t1 t2 t3 t4 t5 t6 t7 t8 command dqs, /dqs dq trc auto precharge begins out0 out2 out1 out3 posted read act nop tras(min.) trp (min.) cl = 3 al = 2 a10 = 1 rl = 5 burst read with auto precharge followed by an activation to the same bank (trp limit) (rl = 5, bl = 4 (al = 2, cl = 3, trtp 2tck)) read act /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 command dqs, /dqs dq nop rl = 5 al = 2 a10 = 1 cl = 3 trp auto precharge begins out0 out1 out2 out3 out4 out5 out6 out7 trc tras (min.) burst read with auto precharge followe d by an activation to the same bank (rl = 5, bl = 8 (al = 2, cl = 3, trtp 2tck))
p3r1ge3jgf, P3R1GE4JGF 61 burst write with auto precharge [writa] if a10 is high w hen a write command is is sued, the w rit e with auto precharge function is eng aged. the ddr2 sdram automatically begins precharge operation after the co mpletion of the burst writes plus write recovery time (twr). the bank un dergoing auto pr ec harge from the c ompletion of t he writ e burst may be reactivated if the following two conditions are satisfied. (1) the data-in to bank activate delay time (twr + trp) has been satisfied. (2) the /ras cycle time (trc) from the prev ious bank activation has been satisfied. in1 in3 /ck ck t0 t1 t2 t3 t4 t5 t6 t7 tm command dqs, /dqs dq twr auto precharge begins completion of the burst write in0 in2 posted writ act nop trp wl = rl ?1 = 2 a10 = 1 trc (min.) burst write with auto precharg e (trc limit) (wl = 2, twr =2) nop ck /ck t0 t3 t4 t5 t6 t7 t8 t9 t10 t11 command dqs, /dqs dq auto precharge begins completion of the burst write in0 in2 nop in1 in3 posted writ act wl = rl ?1 = 4 a10 = 1 trc twr (min.) trp (min.) burst write with auto precharge (tw r + trp) (wl = 4, twr =2, trp=3)
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. 62 writ act /ck ck t0 t2 t4 t6 t8 t10 t3 t5 t7 t9 t11 t12 t13 command dqs, /dqs dq nop wl = rl ? 1 = 4 a10 = 1 twr trp auto precharge begins trc in0 in1 in2 in3 in4 in5 in6 in7 burst write with auto precharge followed by an activation to the same bank (wl = 4, bl = 8, twr = 2, trp = 3)
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 63 refresh requirements ddr2 sdram requires a refr esh of all ro ws in any rolling 64ms interval. each refresh i s generated in one of t wo ways : by an explicit automatic refresh co mmand, or by an internally timed event in self-refresh mode. dividing the number of device rows into the rolling 64 ms interval defines the average refresh interval, trefi, which is a guideline to controllers for distributed refresh timing. automatic refresh command [ref] when /cs, /ras and /cas are he ld low and /we high at the risi ng edge of the clock, the chip enters the automatic refresh mode (ref). all banks of t he ddr2 sdram must be precharge d and idle for a minimum of the prech arge time (trp) bef ore the auto-refresh command (ref) can be appl ied. a n address counter, internal to the d evice, supplies the bank address during the refresh cycle. no control of the external address bus is req uired once this cycle has started. when the refresh cycle has completed, all banks of the ddr2 sdram will be in the precharg ed (idle) state. a delay between the a uto-refresh command (ref) and the ne xt ac tivate command or subs equent auto-refresh command must be greater than or equal to the auto-refresh cycle time (trfc). to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. a maxim um of 8 refresh commands can be posted to any given ddr2 sdram, meaning that the maximum absolute interval between any refr esh command and the next refresh command is 9 trefi. nop pre ck /ck t0 t1 t2 t3 cke command trp vih trfc trfc ref ref nop any command automatic refresh command
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 64 self-refresh command [self] the ddr2 sdram device has a built-in timer to accommodate self-refresh operation. the self-refresh command is defined by having /cs, /ras, /cas and cke held low wi th /we high at the rising edge of the clock. odt must be turned off before issuing s elf-refresh comm and, by either driving odt pin lo w or using emrs command. once the command is registered, cke must be held low to keep the device in self-refresh mode. when the ddr2 sdram has entered self-refresh mode all of the external signals except cke, are dont c are. the clock is internally disabled during self-refresh operation to save power. the user may change the external clock frequency or h alt the e xternal clock o ne clock after self-r efresh entry is registered, however, the cl ock must be restarted and stable before the device can exit self-refresh operation. once se lf-refresh exit command is registered, a delay equal or longer than the txsnr or t xsrd must be satisfied befor e a valid com mand can be issued to the device. cke must remain high for the entire self-refresh exit period txsrd fo r proper operation. nop or deselect commands must be registered on each positive clock edge durin g the self-refresh exit interval. odt should also be turned off during txsrd. notes: 1. device must be in the ?all banks idle? state prior to entering self refresh mode. 2. odt must be turned off taofd before entering self refresh mode, and can be turned on again when txsrd timing is satisfied. 3. txsrd is applied for a read or a read with autoprecharge command. 4. txsnr is applied for any command except a read or a read with autoprecharge command. comand ck t0 t2t1 tm tn cke t3 t4 t5 odt t6 taofd /ck txsnr txsrd trp* tck tch tcl tis tis tis tis tih valid nop nop self nop self-refresh command
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 65 power-down [pden] power-down is synchronously entered when cke is regist ered low (along with nop or deselect comma nd). cke is not allowed to go lo w while mode register or extended mode register command time, or read or write operation is in progress. ck e is allo wed to go lo w while any of other operations such as ro w activation, precharge or auto precharge, or auto-refres h is in pr ogress, but po wer-down idd spec w ill not be appli ed until finishing those operations. timing diagrams are shown in the following pages with details for entry into power-down. the dll should be in a lock ed state when power-down is entered. other wise dll s hould be reset after ex iting power-down mode for proper read operation. if power-down occurs when all banks are idle, this m ode is referre d to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and outp ut buffers, excluding ck, /ck, odt and cke. also the dll is disabled up on entering precharge power-down or slow exit active p ower-down, but the dll is ke pt enabled during fast e xit active power- down. in po wer-down mode, cke lo w and a stable clock signal must be maintai ned at the inputs of the ddr2 sdram, and odt should b e in a valid state but all oth er input sig nals ar e dont care. cke lo w must b e maintained until tcke has been satisfied. power-down duration is limited by 9 times trefi of the device. the power-down state is sync hronously exited when c ke is regist ered high (along with a no p or desel ect command). c ke high must be maintained until tcke ha s been satisfied. a valid, executab le command can be applied with power-down exit latency, txp, txard, or tx ards, after ck e goes high. power-down exit latency is defined at ac characteristics table of this data sheet. ck /ck cke command vih or vil txp, txard,? txards enter power-down mode tcke min exit power-down mode tcke min tihtis tihtis tih tis tih tihtis valid valid valid nop nop valid power-down read to power-down entry ck command cke dq dqs command cke dq dqs /ck al + cl al + cl bl=4 bl=8 t0 tx tx+2 tx+3 tx+4 tx+5 tx+6 t1 t2 tx+1 tx+7 tx+8 tx+9 /dqs /dqs read out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 vih vih cke should be kept high until the end of burst operation. cke should be kept high until the end of burst operation. read operation starts with a read command and t0 tx tx+2 tx+3 tx+4 tx+5 tx+6 t1 t2 tx+1 tx+7 tx+8 tx+9 read
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 66 read with auto precharge to power-down entry ck command cke dq dqs command cke dq dqs al + bl/2 with trtp = 7.5ns and tras min. satisfied /ck start internal precharge al + cl cke should be kept high until the end of burst operation. cke should be kept high until the end of burst operation. al + cl bl=4 bl=8 t0 tx tx+2 tx+3 tx+4 tx+5 tx+6 t1 t2 tx+1 tx+7 tx+8 tx+9 /dqs /dqs reada pre reada out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 al + bl/2 with trtp = 7.5ns and tras min. satisfied pre t0 tx tx+2 tx+3 tx+4 tx+5 tx+6 t1 t2 tx+1 tx+7 tx+8 tx+9 write to power-down entry ck command cke dqs command cke dq dqs /ck wl bl=4 bl=8 /dqs /dqs twtr wl twtr dq in 0 in 1 in 2 in 3 t0 tm+1 tm+3 tx tx+1 tx+2 tx+3 t1 tm tm+2 tx+4 tx+5 tx+6 writ writ in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7 t0 tm+1 tm+3 tm+4 tm+5 tx tx+1 t1 tm tm+2 tx+2 tx+3 tx+4
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 67 write with auto precharge to power-down entry ck /ck wl wr*1 wr*1 ck command cke dq dqs command cke dq dqs /ck bl=4 bl=8 /dqs /dqs writa pre writa in 0 in 1 in 2 in 3 pre wl t0 tm+1 tm+3 tx tx+1 tx+2 tx+3 t1 tm tm+2 tx+4 tx+5 tx+6 note: 1. wr is programmed through mrs t0 tm+1 tm+3 tm+4 tm+5 tx tx+1 t1 tm tm+2 tx+2 tx+3 tx+4 in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 68 refresh command to power-down entry command cke t0 t3 t5 t6 t7 t8 t9 t1 t2 t4 t10 ck /ck cke can go to low one clock after an auto-refresh command t11 ref active command to power-down entry command cke cke can go to low one clock after an active command act precharge/precharge all command to power-down entry command cke cke can go to low one clock after a precharge or precharge all command pre or pall mrs/emrs command to power-down entry command cke mrs or emrs tmrd
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. document : ver.2.1 deutron electronics corp. 69 asynchronous cke low event dram requires cke to be maintain ed high for all va lid operations as defined in this data sh eet. if cke asynchronously drops low during any valid operation dram is not guaranteed to preserve t he contents of array. if this event occurs, memory controller must satisfy dram timing specification tdelay before turning off the clocks. stable clocks must ex ist at the inp ut of dram before cke is raised hig h again. dram must be fully re-initialized (steps 4 thro ugh 13) as described in initialization s equence. d ram is rea dy for normal operation after th e initialization sequence. see ac charac teristics table for tdelay specification tck ck /ck tdelay cke cke asynchronously drops low clocks can be turned off after this point stable clocks
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. 70 burst interruption interruption of a burst read or write cycle is prohibited. no operation command [nop] the no operation command s hould be used in cases when the ddr2 sdram is in an idle or a wait state. the purpose of the no operati on command is to prevent the d dr2 sdram from registering any unwanted commands between operations. a no operation command is registered when /cs is low with /ras, /cas, and /we held high at the rising edge of the clock. a no oper ation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. deselect command [desl] the deselect command perf orms the same functio n as a no operation command. deselect command occurs when /cs is brought high at the rising edge of the clock, the /ras, /cas, and /we signals become dont cares. input clock frequency change during precharge power-down ddr2 sdram input clock frequency can be changed under following condition: ddr2 sdram is in precharged power-down mode. odt must be tur ned off an d cke must be at logic low level. a minimum of 2 clocks must be waited after cke goes lo w before clock frequency may change. sdram input clock frequency is allowed to change only within minimum and maximum operating frequency specified for the particul ar speed grade. during input clock frequency change, odt and cke must be held at stable low levels. once input clock frequency is changed, stable new clocks must be provided to dram before precharge power-down may be exited and dll mus t be reset via emrs after prech arge power-down exit. depe nding on new clock frequency an additional mrs command may need to be issued to appropriately set the wr, cl and s oon. during dll relock period, odt must remain off. a fter the dll lock time, the dram is ready to operate with new clock frequency. clock frequency change in precharge power-down mode ck cke t0 t4 tx+1 ty ty+1 ty+2 t1 t2 tx /ck ty+3 tz trp txp taofd stable new clock before power down exit odt is off during dll reset minmum 2 clocks required before changing frequency odt command ty+4 nop nop nop nop dll reset nop valid 200 clocks frequency change occurs here
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. 71 package drawing 60-ball fbga solder ball: lead free (sn-ag-cu) 8.0 0.1 index mark 9.5 0.1 0.1 s 0.2 s 1.20 max. 0.35 0.05 s b a index mark 0.8 8.0 1.6 6.4 unit: mm 0.2 s b 60- 0.45 0.05 0.15 m sa b eca-ts2-0225-01 0.2 s a 0.8
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. 72 84-ball fbga solder ball: lead free (sn-ag-cu) 84- 0.45 0.05 8.0 0.1 index mark 12.5 0.1 0.1 s 0.2 s 1.20 max. 0.35 0.05 s b a index mark 0.8 6.4 unit: mm 0.2 s b 0.15 m sab eca-ts2-0224-01 0.2 sa 0.8 1.6 11.2
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. 73 recommended soldering conditions please consult with our sales offices for soldering conditions of the ede11xxajbg. type of surface mount device p3r1ge3jgf : 60-ball fbga < lead free (sn-ag-cu) > P3R1GE4JGF : 84-ball fbga < lead free (sn-ag-cu) >
p3r1ge3jgf, p3r1ge4gf document : ver.2.1 deutron electronics corp. 74 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
p3r1ge3jgf, P3R1GE4JGF document : ver.2.1 deutron electronics corp. 75 m no part of this document may be copied or reproduced in any form or by any means without the prior written consent of deutron electronics corp. deutron does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of deutron electronics corp. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of deutron electronics corp. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer . deutron electronics corp assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] be aware that this product is for use in typical electronic equipment for general-purpose applications. deutron electronics corp. makes every attempt to ensure that its products are of high quality and reliability. however, this product is not intended for use in the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury . customers are instructed to contact deutron's sales office before using this product for such applications. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by deutron including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. deutron electronics corp. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating deutron electronics corp. products does not cause bodily injury, fire or other consequential damage due to the operation of the deutron electronics corp. product. [usage environment] usage in environments with special characteristics as listed below was not considered in the design. accordingly, our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below. example: 1) usage in liquids, including water, oils, chemicals and organic solvents. 2) usage in exposure to direct sunlight or the outdoors, or in dusty places. 3) usage involving exposure to significant amounts of corrosive gas, including sea air , cl 2 , h 2 s, nh 3 , so 2 , and no x . 4) usage in environments with static electricity, or strong electromagnetic waves or radiation. 5) usage in places where dew forms. 6) usage in environments with mechanical vibration, impact, or stress. 7) usage near heating elements, igniters, or flammable items. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign t rade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party , or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.

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